Sintegra Inc. ยท 3 weeks ago
Physical Design Engineer
San Francisco Bay Area
Full-time
Hybrid
Mid LevelSintegra Inc. is seeking an experienced and highly skilled Block-Level Design Engineer to join their innovative team. The ideal candidate will excel in RTL-to-GDSII design processes and work on cutting-edge designs for lower nodes (3nm, 4nm, 5nm).
SemiconductorSoftware
Responsibilities
Perform block-level design from RTL-to-GDSII
Handle synthesis, floor-planning, place & route, timing/EMIR/PV closure, and signoff
Utilize the Synopsis Implementation tool suite (Fusion Compiler, ICC2)
Implement controllers for High-Speed IO IPs
Conduct structural implementation, including datapaths, bus planning, and routing
Design with multi-power domains
Develop and maintain scripts using TCL and Python
Qualification
Required
Proficiency with Synopsis Implementation tool suite (Fusion Compiler, ICC2)
Experience in structural implementation of datapaths, bus planning, and routing
Strong scripting skills in TCL and Python
Familiarity with multi-power domain design
Experience with controllers for High-Speed IO IPs
Preferred
Knowledge of lower-node technologies (3nm, 4nm, 5nm) is a strong advantage
Company
Sintegra Inc.
Backed by 25+ years of deep silicon expertise, Sintegra is the trusted chip design partner to both Fortune 500 leaders and fast-moving startups - from Google, Meta, and Nvidia to Celestial AI, Cerebras, and Rivos.
Founded in 1999
11-50 employees
H1B Sponsorship
Sintegra Inc. has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (18)
2024 (7)
2023 (4)
2022 (3)
2021 (2)
Funding
Current Stage
Early StageLeadership Team
Bharat G.
President & CEO
Company data provided by crunchbase