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Amazon · 8 hours ago

ASIC Design Engineer, Amazon Leo

Austin, TX

Full-time

Onsite

Mid, Senior Level

$130K/yr - $213K/yr

5+ years exp

Amazon is launching a constellation of Low Earth Orbit satellites to provide broadband connectivity to underserved communities. The ASIC Design Engineer will be responsible for RTL design and development, integration of subsystems, and gate-level simulation to ensure ASIC functionality and timing.

Artificial Intelligence (AI)DeliveryE-CommerceFoundational AIRetail

No H1B

U.S. Citizen Only

Responsibilities

RTL Design and development of custom blocks

Integration of large subsystems

Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic errors, and propose solutions. Work closely with design and verification engineers to validate fixes and ensure design closure

Facilitate seamless integration across Firmware, RTL, Platform Software, and Platform Drivers

Develop Debug tools: RTL Emulation, silicon bring-up, and functional validation

Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets

Define, configure and integration SoC Subsystems

Contribute to the SoC floor planning effort

Define and develop any necessary support logic

Configure, instantiate and integrate 3rd party IP blocks

Understand low power design & the impact of DFT on the blocks

Perform initial synthesis & timing analysis

Assist verification team in unit verification including test plan development

Assist with debug and bring-up

Qualification

Verilog RTL developmentSoC designDigital designGate Level SimulationDebug tools developmentTeam collaborationProblem solving

Required

5+ years of non-internship professional Verilog RTL development experience

5+ years of programming with at least one Verilog RTL programming language experience

5+ years of leading design or architecture (design patterns, reliability and scaling) of new and existing systems experience

5+ years of digital design experience, preferably in SoC design and implementation

Preferred

5+ years of full Verilog RTL development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience

Master's degree in computer science or equivalent