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Tenstorrent · 4 days ago

Sr Staff CPU Core/Unit Verification Engineer, Functional Safety

Austin, Texas, United States

Full-time

Hybrid

Senior Level, Lead/Staff

$100K/yr - $500K/yr

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. They are seeking a passionate and detail-oriented Design Verification Engineer to join their Functional Safety IP team, focusing on verifying safety-critical IPs designed to meet ISO 26262 and similar safety standards.

Application Specific Integrated Circuit (ASIC)Artificial Intelligence (AI)ElectronicsMachine LearningSemiconductor

Comp. & Benefits

No H1B

U.S. Citizen Only

Responsibilities

Ability to build C++/UVM environments and author safety-focused test plans

Experience with fault injection, resilience testing, or safety diagnostics

Hands-on experience with Synopsys VC Z01X, Siemens Tessent or Cadence Safety Verification for fault simulation and analysis

Work closely with safety architects and designers to validate safety mechanisms and Analyze fault simulation results to measure and report diagnostic coverage (SPFM, LFM, PMHF)

Ensure traceability of safety requirements from PRD → RTL → testbench → Stimulus → results

Qualification

SystemVerilogC++UVMISO 26262Fault injectionResilience testingSafety diagnosticsSynopsys VC Z01XSiemens TessentCadence Safety VerificationTeam playerClear communicationIndependent work

Required

Experienced DV engineer with SystemVerilog, C++ and UVM expertise

Strong interest in safety-critical design and understanding of ISO 26262 ISO (ASIL levels B–D) or other safety standards

Able to work independently and deliver in a highly accountable environment

Team player who communicates clearly and thrives in cross-functional teams

Ability to build C++/UVM environments and author safety-focused test plans

Experience with fault injection, resilience testing, or safety diagnostics

Hands-on experience with Synopsys VC Z01X, Siemens Tessent or Cadence Safety Verification for fault simulation and analysis

Work closely with safety architects and designers to validate safety mechanisms and analyze fault simulation results to measure and report diagnostic coverage (SPFM, LFM, PMHF)

Ensure traceability of safety requirements from PRD → RTL → testbench → Stimulus → results