Cirrus Logic · 1 day ago
Summer Intern - Mixed Signal Modeling & Verification Engineer
Cirrus Logic is a leader in mixed-signal processing, renowned for its innovative solutions and inclusive culture. The company is seeking a creative and hardworking engineering intern to join their Analog/Mixed-Signal Verification, Modeling and Methodology Team, where the intern will collaborate with experienced engineers to develop and validate System Verilog models and contribute to product development.
Enterprise SoftwareReal TimeSoftwareSpeech Recognition
Responsibilities
You will contribute to a team that performs verification planning and AMS simulation on full custom ASICs for audio processing applications
Develop behavioral models using SystemVerilog real number modeling (sv-rnm), user-defined types(sv-udt), & Verilog AMS
Independent Interpretation of analog circuit schematics into abstract models
Performing regression debug support and other flow/infrastructure development
Qualification
Required
Actively pursuing a Bachelors, Masters, or PhD in Electrical Engineering or Computer Engineering
Good understanding of analog integrated circuit design
Experience with System Verilog real number modeling (RNM) modeling and/or Verilog-A behavioral modeling
Organized and detailed with strong communication skills
Possess outstanding analytical and problem-solving skills
Results-oriented and ability to operate in dynamic environment
Preferred
Python skills would be highly desirable
Company
Cirrus Logic
Cirrus Logic is an industry leader in low-power audio and high-performance mixed-signal processing technology that creates immersive user experiences for the world’s top mobile and consumer applications.
Funding
Current Stage
Late StageTotal Funding
$5.8M2017-04-01Acquired
2016-02-11Debt Financing· $0.23M
2015-03-24Series Unknown· $0.58M
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