Draper · 5 days ago
Senior UVM Digital Verification Engineer
Cambridge, MA
Full-time
Onsite
Mid, Senior Level
$82K/yr - $206K/yr
5+ years expDraper is an independent, nonprofit research and development company headquartered in Cambridge, MA. They are seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs, applying modern verification strategies to complex digital and mixed-signal designs.
Defense & Space
No H1B
Security Clearance RequiredU.S. Citizen Only
Responsibilities
Performs analysis approaches for a particular problem and independently execute assignments
Independently execute system engineering lifecycle assignments; concept and architecture design, integration, testing and operation
Drive solutions to complex problems with limited direction – contribute to task planning and test development, propose ways forward, and adapt appropriately to changes in program requirements
Demonstrated ability to lead small teams (fewer than five people). Seeks to align team towards program goals and builds trust within the team
Able to provide insight and suggest design modifications based on analysis outcomes, and to apply analysis techniques across a range of technical challenges
Identify program/system-level technical risks and develop and execute mitigation strategies for them
Actively mentor less experienced engineers and provide thoughtful, constructive feedback
Work in a collaborative multidisciplinary environment including stakeholders and external partners
Contribute to translation of requirements into technical and architectural decisions
Develop verification and test plans
Develop UVM Agents for proprietary buses
Instantiate VIPs for industry standard buses
Work in both block-level/chip-level UVM testbench environment
Work with RTL designers to resolve simulation issues
Implement cover groups according to design requirements
Work on code and functional coverage closures to achieve 100%
Perform code reviews and to mentor junior engineers in the group
Fluent in System Verilog including SVA
Recent experience with UVM/UVMF
Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS)
Familiarity with at least one IEEE bus standardExperience with DDR3/DDR4, Amba Axi protocols
Firm grasp of constrained-random testing and coverage-driven verification
Experience with formal analysis
Practice using Python, Perl, Bash or other scripting languages
Ability to work in a Linux environment
Strong analysis and problem-solving skills
Qualification
Required
Bachelor's degree in Aerospace, Electrical, Mechanical, or other relevant Engineering field
Requires 5-7 years experience in systems analysis or related
Experience in integrating descriptive modeling tools with other simulation tools
Excellent mathematical skills
Thorough understanding of engineering theories and procedures
Ability to collaborate within a diverse and multidisciplinary team
Excellent verbal and written communication skills
Excellent organizational skills and attention to detail
Excellent time management skills with the proven ability to meet deadlines
Demonstrated knowledge of multiple problem domains, with ability to quickly become knowledgeable in new domains
Identify and develop relevant modeling and analysis techniques, and develop or integrate multi-domain qualitative models
Ability to present results that support system-level analysis, performance trade-offs, and decision-making
The ability to communicate technical concepts effectively with customers, engineers, managers, and other stakeholders of all relevant disciplines
Flexibility to multi-task and adapt to evolving priorities
Develop verification and test plans
Develop UVM Agents for proprietary buses
Instantiate VIPs for industry standard buses
Work in both block-level/chip-level UVM testbench environment
Work with RTL designers to resolve simulation issues
Implement cover groups according to design requirements
Work on code and functional coverage closures to achieve 100%
Perform code reviews and to mentor junior engineers in the group
Fluent in System Verilog including SVA
Recent experience with UVM/UVMF
Firm grasp of constrained-random testing and coverage-driven verification
Experience with formal analysis
Practice using Python, Perl, Bash or other scripting languages
Ability to work in a Linux environment
Strong analysis and problem-solving skills
Applicants selected for this position will have or be able to obtain and maintain a government security clearance
Preferred
Master's degree preferred
Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS)
Familiarity with at least one IEEE bus standard
Experience with DDR3/DDR4, Amba Axi protocols
Benefits
Workplace flexibility
Employee clubs ranging from photography to yoga
Health and finance workshops
Off site social events
Discounts to local museums and cultural activities
Company
Draper
We Engineer Solutions for the Nation’s Toughest Problems As an independent nonprofit engineering innovation company, Draper provides engineering services directly to government, industry, and academia.
1001-5000 employees
Funding
Current Stage
Late StageLeadership Team
Jerry Wohletz
President and Chief Executive Officer
Brenan McCarragher
Chief Technology Officer
Recent News
Business Journals
2024-03-28
2024-02-28
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