Interconnect RTL Design Engineer jobs in United States
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AMD ยท 4 months ago

Interconnect RTL Design Engineer

Advanced Micro Devices, Inc is a company focused on transforming lives with technology. They are seeking an Interconnect RTL Design Engineer to help build the next generation scalable coherent interconnect for connectivity between CPU, GPU, and special purpose accelerators, working on a variety of products across multiple markets.

AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor
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Growth Opportunities
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H1B Sponsor Likelynote

Responsibilities

Early architectural/performance exploration through micro-architectural definition and design
Optimize the design to meet power, performance, area and timing requirements
Write easily readable and synthesizable system Verilog RTL
Run unit level testing to deliver quality code to the Design Verification Team
Create assertions to improve coverage and cover points to analyze coverage of the design
Build testbench components to support the next generation IP
Maintain or improve current test libraries to support IP level testing
Create hardware emulation build to verify the IP functional performance
Create well written block level design documentation
Participate in post silicon functional and performance debug and tuning
Provide technical support to other teams such as verification and physical design teams
Mentor junior engineers

Qualification

System Verilog RTLDigital designProcessor architectureVerilogC/C++Debugging skillsAnalytical skillsCommunication skillsTeam player

Required

Passion for modern, complex processor architecture, digital design, and verification
Excellent communication skills
Experience collaborating with other engineers located in different sites/time zones
Strong analytical and problem-solving skills
Willingness to learn and take on problems
Early architectural/performance exploration through micro-architectural definition and design
Optimize the design to meet power, performance, area and timing requirements
Write easily readable and synthesizable system Verilog RTL
Run unit level testing to deliver quality code to the Design Verification Team
Create assertions to improve coverage and cover points to analyze coverage of the design
Build testbench components to support the next generation IP
Maintain or improve current test libraries to support IP level testing
Create hardware emulation build to verify the IP functional performance
Create well written block level design documentation
Participate in post silicon functional and performance debug and tuning
Provide technical support to other teams such as verification and physical design teams
Mentor junior engineers
Bachelors or Masters degree in computer engineering/Electrical Engineering

Preferred

Proven experience designing logic blocks in CPU, GPU, NOC, or cache designs
Strong understanding of digital electronics and high-speed designs(>1GHz)
Strong understanding of multi-processor coherency, memory ordering, i/o ordering, interrupts, MMU and caches
Excellent knowledge of Verilog and System Verilog
Good debugging and analytical skills
Exposure to Design for Test, understanding of scan concepts and writing DFT friendly RTL
Working knowledge of C, C++ and a scripting language like Perl or Python

Benefits

Benefits offered are described: AMD benefits at a glance

Company

Advanced Micro Devices is a semiconductor company that designs and develops graphics units, processors, and media solutions.

H1B Sponsorship

AMD has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (836)
2024 (770)
2023 (551)
2022 (739)
2021 (519)
2020 (547)

Funding

Current Stage
Public Company
Total Funding
unknown
Key Investors
OpenAIDaniel Loeb
2025-10-06Post Ipo Equity
2023-03-02Post Ipo Equity
2021-06-29Post Ipo Equity

Leadership Team

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Lisa Su
Chair & CEO
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Mark Papermaster
CTO and EVP
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Company data provided by crunchbase