Tenstorrent · 3 months ago
DFT/DFD Design Verification Engineer, Chiplets (contractor)
Boston, Massachusetts, United States
Contract
Onsite
Mid Level
$100K/yr - $500K/yrTenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations and cost efficiency. They are seeking an experienced DFT/DFD Design Verification Engineer to support the validation of advanced test architectures in high-performance SoCs, focusing on verifying DFT and DFD logic to ensure manufacturability and debuggability.
AI InfrastructureApplication Specific Integrated Circuit (ASIC)Artificial Intelligence (AI)ElectronicsMachine LearningSemiconductor
Responsibilities
Define and execute verification plans for DFT/DFD features such as boundary scan, scan chains, and debug logic
Develop UVM-based or directed tests to validate IEEE 1149.x (JTAG), 1500 (iJTAG), and 1687 (IJTAG) compliant implementations
Verify integration and functionality of ICL (Instrument Connectivity Language) and PDL (Procedure Description Language) content for instrument and test control
Simulate and debug DFT/DFD RTL and gate-level designs using industry-standard simulators
Collaborate with DFT architecture and implementation teams to ensure functional correctness, performance, and alignment with manufacturability goals
Drive coverage closure, including code coverage and functional coverage, across all DFT/DFD blocks
Work with post-silicon validation and ATE teams to ensure test vector portability and alignment between simulation and silicon
Qualification
Required
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
Proven experience in design verification for DFT/DFD architectures in complex SoC environments
Hands-on experience with IEEE JTAG-related standards: 1149.1, 1500, and 1687
Proficiency in writing and debugging ICL and PDL files for test generation and instrumentation control
Experience using Siemens Tessent tool suite for scan insertion, ATPG, IJTAG, and pattern generation
Solid understanding of RTL verification flows and simulation methodologies
Proficiency in Verilog/SystemVerilog and scripting (Python, Perl, TCL)
Strong analytical and debugging skills with attention to detail and documentation
Experience with UVM-based testbench environments for DFT/DFD verification
Preferred
Experience with UVM-based testbench environments for DFT/DFD verification
Familiarity with scan compression, LBIST/MBIST, and test access architectures
Exposure to gate-level simulations and post-silicon test bring-up workflows
Strong collaboration skills with ability to work across architecture, design, and ATE teams
Knowledge of scan diagnosis and failure analysis workflows is a plus
Benefits
Highly competitive compensation package
Benefits
Company
Tenstorrent
Tenstorrent develops AI hardware and software solutions for data processing and machine learning application.
Founded in 2016
501-1000 employees
H1B Sponsorship
Tenstorrent has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (52)
2024 (42)
2023 (17)
2022 (18)
2021 (28)
Funding
Current Stage
Late StageTotal Funding
$1.03BKey Investors
FidelityEPIQ Capital GroupEclipse Ventures
2024-12-02Series D· $693M
2023-08-02Series Unknown· $100M
2021-05-20Series C· $200M
Leadership Team
Jim Keller
CEO
Keith Witek
Chief Operating Officer and Board Member
Recent News
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