Qualcomm · 2 weeks ago
ASIC Timing and Methodology Engineer
San Diego, CA
Full-time
Onsite
Mid, Senior Level
$140K/yr - $210K/yr
3+ years expQualcomm Technologies, Inc. is a leader in the mobile and computing technology space, seeking a Timing Engineer to contribute to the design and validation of innovative SOC products. The role involves working with various teams to achieve timing closure and facilitate STA methodology, while also requiring strong programming skills and knowledge of ASIC design processes.
Artificial Intelligence (AI)Generative AISoftwareTelecommunicationsWireless
Responsibilities
Play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT markets
Work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4nm and beyond (process technologies)
Work with physical design team (and other teams) on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation
Responsible for Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim) for PVT corners validation and STA vs spice correlation
Timing package validation across advanced process technologies using PT/PT-SI and Tempus
Facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus and best in class timing ECO tools
Work on timing sign off specification for different projects and support timing sign off for complex SOC’s
Hands on contribution for STA timing sign off
Understand all kind of intricate timing paths (digital, analog, mixed signal), timing constraints and provide solutions if required
Good understanding of RTL to GDS digital flow
Knowledge of DC/DCT/DCG/Genus/Oasis, ICC2/Fusion/Innovus/Aprisa, RedHawk/SeaHawk/Voltus is a plus
Good execution knowledge
Contribution should improve timing convergence process across the company, design PPA, yield and support new advanced process technologies bring-up from pdk to vlsi design production
Good programming skills Python, Perl, TCL, Unix shell , C/C++
ML modeling experience is a plus
Qualification
Required
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
Good understanding of RTL to GDS digital flow
Good programming skills Python, Perl, TCL, Unix shell, C/C++
Preferred
Knowledge of DC/DCT/DCG/Genus/Oasis, ICC2/Fusion/Innovus/Aprisa, RedHawk/SeaHawk/Voltus is a plus
ML modeling experience is a plus
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
10001+ employees
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
Leadership Team
Cristiano Amon
President and Chief Executive Officer
I
Isaac Eteminan
CEO
Recent News
Android Authority
2026-01-09
2026-01-09
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