Astera Labs · 3 months ago
Lead Package Design Engineer
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
$176K/yr - $230K/yr
6+ years expAstera Labs is a fabless semiconductor company that develops connectivity solutions for AI infrastructure. They are seeking a Lead Package Design Engineer to take ownership of package design and layout for their connectivity products, ensuring performance optimization and guiding junior designers.
AutomotiveElectronicsIntelligent SystemsSemiconductor
Responsibilities
Take ownership of package design and layout for Astera Labs’ portfolio of connectivity products
Drive package substrate design from definition to tape-out, including performance optimization, design for manufacturing, and sign-off verification
Provide technical guidance within the package design team: mentoring junior designers, guiding best practices in APD, reviewing design work for quality and consistency
Work closely with SI/PI, product engineering, and hardware teams to ensure first-pass success
Help shape design flows, champion productivity improvements, and represent package design expertise in cross-functional discussions
Qualification
Required
BS/MS in Engineering (Electrical, Mechanical, Materials Science, Physics, or related field)
6+ years of experience in Cadence APD/SiP with a track record of independently designing and releasing FCBGA/FCCSP packages from concept to tape-out
Proven experience leading package design efforts, reviewing and mentoring other designers, and setting technical directions
Deep understanding of BGA substrate technologies, stackups, design rules, and assembly processes
Familiarity with package reliability, SI/PI, and design sign-off methodologies
Entrepreneurial, open-minded, and hands-on work ethic with the ability to drive multiple priorities in a dynamic environment
Strong collaboration and communication skills to work effectively across functions and influence outcomes
Expert proficiency in Cadence APD/SiP (this is a must have). Able to design large-body BGAs from concept through tape-out with minimal guidance
Strong knowledge of package BOM integration, layer stackup, padstacks, constraint setup (physical and electrical), SMT component design, and optimization based on SI/PI feedback
Experience running and interpreting DRC/DRV/LVS/DFM checks, generating documentation, and releasing Gerbers/artwork
Ability to conduct feasibility studies such as fan-out, mock-ups, and layer/package size reduction
Understanding of package manufacturing flow, supply chain considerations, reliability, and risk management
Technical leadership in driving new APD design flows, methodologies, and automation (working with vendors or through scripting)
Preferred
Multi-chip, interposer, 2.5D or heterogeneous package design experience is a plus
Proficiency in scripting languages for design and reporting automation is a plus
Company
Astera Labs
Astera Labs is a semiconductor company that provides connectivity solutions for intelligent systems.
201-500 employees
H1B Sponsorship
Astera Labs has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (50)
2024 (44)
2023 (17)
2022 (26)
2021 (14)
2020 (7)
Funding
Current Stage
Public CompanyTotal Funding
$206.35MKey Investors
Fidelity
2024-03-20IPO
2022-11-17Series D· $150M
2021-09-27Series C· $50M
Leadership Team
Jitendra Mohan
CEO
Casey Morrison
Chief Product Officer, Co-Founder
Recent News
The Motley Fool
2026-01-07
2025-12-29
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