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Marvell Technology · 2 weeks ago

Principal Engineer, Design Verification

Santa Clara, CA

Full-time

Onsite

Lead/Staff

$147K/yr - $220K/yr

8+ years exp

Marvell Technology is a leader in semiconductor solutions that power data infrastructure across various domains. The Principal Engineer, Design Verification will architect and develop a functional verification environment, contributing to the development of test plans and verification methodologies.

DSPInternet of ThingsManufacturingSemiconductorWireless

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Writing a verification test plan that employs random techniques, directed testing and coverage analysis to thoroughly check functional correctness and performance

Developing a testbench using UVM, System Verilog, C/C++, and DPI

Verification at different levels of hierarchy including block/unit, subsystem, and SOC levels

Working closely with logic designers to ensure the test plan is complete, debug simulation failures, and resolve issues

Technical leadership of teams and mentoring of junior engineers

Qualification

SOC verificationUVMSystem VerilogC/C++PythonEDA toolsIndependent learnerProactive problem solvingEffective communicationTeamwork skillsAttention to detail

Required

BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering, 8+ years of relevant professional experience

Strong background in creating test plans and designing test bench architectures that are hierarchical, reusable and scalable

Strong background in SOC verification and test bench development using UVM and System Verilog, object oriented programming, and constrained random methods

Experience with EDA verification and debugging tools, scripting languages such as Python or Perl, and revision control systems

Effective communication and teamwork skills

Mindset for high quality and attention to detail

Independent learner, proactive in problem solving and finding solutions