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Comtech Telecommunications Corp. · 3 months ago

Senior FPGA Engineer III

Chandler, AZ

Full-time

Onsite

Senior Level

5+ years exp

Comtech Telecommunications Corp. is a leading global technology company providing innovative communication solutions. They are seeking a Senior FPGA Engineer III to design, develop, document, debug, and test FPGA SoC systems, while effectively collaborating with team members and engineering management.

Developer PlatformInformation TechnologyInternetManufacturingPublic RelationsTelecommunicationsWireless

No H1B

Security Clearance Required

Responsibilities

Design, develop, document, debug and test FPGA SoC systems; including:

IP Integration into FPGA Projects (synthesis/implementation)

High-Performance FPGA IP (VHDL/SystemVerilog)

Userspace Drivers for FPGA IP (C++)

Firmware for Embedded Microcontrollers (C)

Utilize strong communication skills to effectively work and communicate with team members and engineering management

Qualification

FPGA/ASIC SoC designAltera QuartusXilinx VivadoStatic Timing AnalysisC++CGIT version controlAMBA-compliant AXIMicrosoft Office ToolsCommunication skillsCross-functional teamwork

Required

Strong digital design engineer with FPGA/ASIC SoC design experience

Strong FPGA Implementation with Altera Quartus or Xilinx Vivado

Experience designing/debugging SoC systems with AMBA-compliant AXI and APB interfaces

Experience designing fmax-optimized, high-throughput, pipelined AXI-Stream IP

Capable of creating RTL simulations to identify and resolve most issues before hardware tests

Knowledgeable in Static Timing Analysis (STA) and Synopsis Design Constraints (SDC)

Experience analyzing STA reports and post-synth netlist/placement to resolve failing paths

Experience contributing to schematic capture and layout for FPGA portions of PCB designs

Experience implementing at least one Gigabit Transceiver Protocol: PCI Express, Interlaken, USB SuperSpeed, 1000BASE-X/SGMII, 10GBASE-R, 40GBASE-4, 100GBASE-R4

Experience implementing Network Protocols, such as: L1: IEEE 802.3, Cisco, Q/SFP+ MSA standards for Ethernet (1G to 100G), L2/L3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP, L4: VITA 49.2, IEEE-ISTO 4900 Digital IF Interoperability Standard (DIFI) and/or eCPRi

Proficient in SW development with C, C++ and GIT version control

Proficient in Microsoft Office Tools (Word, Excel, PowerPoint, Visio, etc.)

Demonstrated experience supporting multi-disciplinary, cross functional and matrixed teams

Bachelors in Electrical or Computer Engineering (or related degree)

5+ years of FPGA/ASIC SoC design experience