Principal Digital Verification Engineer/Senior Principal Digital Verification Engineer jobs in United States
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Northrop Grumman Australia · 3 months ago

Principal Digital Verification Engineer/Senior Principal Digital Verification Engineer

Northrop Grumman Australia is seeking a Principal Digital Verification Engineer/Senior Principal Digital Verification Engineer to join their team. The role involves performing functional verification of ASIC and FPGA product development using modern verification methods and tools, collaborating with design and verification engineers to achieve project goals.

Defense & Space
badNo H1BnoteSecurity Clearance RequirednoteU.S. Citizen Onlynote

Responsibilities

Work closely with design and verification engineers and will utilize your knowledge of modern verification methods, tools and techniques
Perform functional verification of register transfer level (RTL) code of a complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilog
Development of testbench, tests, verification IP (VIP), verification models, coverage models, extensive simulation and debug, code coverage and functional coverage, generation and analysis of reports and metrics, documentation etc
Ability to operate in a team environment and collaborate across the different teams as required to accomplish the goals

Qualification

FPGA verificationASIC verificationUVMSystemVerilogTestbench developmentRTL debugObject-oriented programmingScripting languagesDigital signal processingTeam collaboration

Required

Bachelor's degree with 5 years of experience, a Master's degree with 3 years of experience or a PhD with 0 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree
U.S Citizenship is required
The ability to obtain/maintain an Active DoD secret clearance and Special Program Access (SAP)
3 years of experience with FPGA or ASIC verification using UVM
Experience developing testplans, participating in reviews, test development and RTL debug
Bachelor's degree with 8 years of experience, a Master's degree with 6 years of experience or a PhD with 3 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree
U.S Citizenship is required
The ability to obtain/maintain an Active DoD secret clearance and Special Program Access (SAP)
3 years of experience with FPGA or ASIC verification using UVM
Experience developing testplans, participating in reviews, test development and RTL debug

Preferred

Advanced Degree with at least 3+ years of professional experience in related industry
Experience with data structures, object oriented programming languages and concepts
Experience with Verification IP integration and/or development
Experience with a coverage-driven verification methodology from planning through closure
Knowledge of industry standard bus or I/O interfaces
Experience with SystemVerilog Assertions (SVA)
FPGA/ASIC design and/or development process experience
Experience with scripting languages (Bash, Perl, Python, Tcl, Makefile)
Knowledge of digital signal processing

Benefits

Medical, Dental & Vision coverage
401k
Educational Assistance
Life Insurance
Employee Assistance Programs & Work/Life Solutions
Paid Time Off
Health & Wellness Resources
Employee Discounts

Company

Northrop Grumman Australia

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Northrop Grumman Australia is the Australia-based arm of Northrop Grumman Corporation and committed to generating long-term prosperity, investing in advanced Research & Development, sovereign and exportable Intellectual Property, high-quality jobs and long-term technology leadership across the Commonwealth.

Funding

Current Stage
Late Stage
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