Lead Applications Engineer – DDR Design IP jobs in United States
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Cadence · 3 months ago

Lead Applications Engineer – DDR Design IP

positionSAN JOSE
timeFull-time
remoteOnsite
senioritySenior Level, Lead/Staff
money$103K/yr - $191K/yr
date3+ years exp

Cadence is a company that develops industry-leading IPs for various markets, including data centers and automobiles. They are looking for a Lead Applications Engineer to architect memory solutions using Cadence DDR IP, providing technical presales support and collaborating with sales and R&D teams.

AerospaceElectronic Design Automation (EDA)HardwareMobileSemiconductorSoftware
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Growth Opportunities
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H1B Sponsor Likelynote

Responsibilities

Technical presales of Memory IP
Present Cadence’s IP portfolio and capabilities to prospective customers
Work closely with IP Sales staff, marketing and R&D teams to win opportunities
Performance evaluations of Cadence memory IP and development of related infrastructure
Serve as a product expert in memory controller and PHY IPs and protocols
Provide quick-turn product specific technical support to customers, field teams, definers and designers
Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts for internal and/or external publication
Travel to customer sites may be required occasionally

Qualification

DRAM protocolsASIC flowRTL/VerilogSimulation toolsMemory controllerMemory PHYIndividual leadershipPresentation skillsCommunication skills

Required

BS in EE, CE or related equivalent with 5+ years of work experience or MS in EE, CE or equivalent with 3+ year of work experience
Knowledge of one or more DRAM protocols – DDR4/5, LPDDR4/5/5X, HBM2/3, GDDR6
Experience with simulation and synthesis tools
Strong knowledge of ASIC flow, RTL/Verilog
Individual leadership and initiative to manage pre-sales accounts
Excellent presentation skills and verbal/written communication skills is a must

Preferred

Experience on memory subsystem verification and/or performance analysis
Knowledge of System Verilog and FPGA design
Knowledge of AXI, DFI and MIPI protocols
Working knowledge of memory controller and memory PHY

Benefits

Paid vacation and paid holidays
401(k) plan with employer match
Employee stock purchase plan
A variety of medical, dental and vision plan options
And more.

Company

Cadence

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Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems.
dateFounded in 1988
location
San Jose, California, USA
people-size10001+ employees
web-link
https://www.cadence.com

H1B Sponsorship

Cadence has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (306)
2024 (221)
2023 (282)
2022 (330)
2021 (233)
2020 (209)

Funding

Current Stage
Public Company
Total Funding
unknown
1998-02-20IPO

Leadership Team

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Paul Cunningham
Senior Vice President and General Manager
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Tom Beckley
Senior Vice President, Custom IC & PCB Group
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Recent News

Morningstar.com
Cadence Announces Fourth Quarter and Fiscal Year 2025 Financial Results Webcast
2026-01-07
MarketScreener
Cadence Design Systems to integrate CUDA X technology into chip design software - Nvidia CEO at CES
2026-01-06
Business Wire
Cadence Launches Partner Ecosystem to Accelerate Chiplet Time to Market
2026-01-06
Company data provided by crunchbase