Avicena Tech · 3 months ago
ASIC Digital Design Engineer
Sunnyvale, CA
Full-time
Onsite
Senior Level
5+ years expAvicena Tech is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. They are seeking a skilled ASIC Digital Design Engineer to develop high-speed, low-power digital integrated circuits for next-generation photonics and optical interconnect solutions.
ElectronicsIndustrial ManufacturingManufacturingSemiconductor
Responsibilities
RTL Design and Coding: Develop and implement high-quality, efficient Register Transfer Level (RTL) code using Verilog or SystemVerilog for complex digital modules, ensuring compliance with architectural specifications
Design Verification: Collaborate closely with the verification team to define test plans, review coverage, and debug functional and timing issues using simulation tools
Synthesis and Timing Closure: Perform logic synthesis and work on timing constraints, static timing analysis (STA), and timing closure to meet frequency goals, power targets, and area requirements
DFT Insertion: Incorporate Design-for-Test (DFT) structures, including SCAN and BIST, to ensure testability and high-quality manufacturing
Linting and CDC: Perform extensive linting checks and Clock/Reset Domain Crossing (CDC/RDC) analysis to ensure robust, clean, and reliable RTL code
Documentation: Generate clear, detailed technical documentation for design specifications, implementation details, and verification results
Collaboration: Interface with architecture, verification, physical design (backend), and silicon validation teams to ensure seamless integration and successful tape-out
Qualification
Required
Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
Experience: 5+ years of industry experience in frontend digital IC design
Expertise in HDLs: Strong proficiency in Verilog or SystemVerilog for complex ASIC/SoC design
ASIC Flow Knowledge: Solid understanding of the complete ASIC design flow from specification to tape-out
Tool Experience: Hands-on experience with industry-standard EDA tools for simulation, synthesis (e.g., Cadence Genus, Synopsys Design Compiler), STA (e.g., Cadence Tempus, Synopsys PrimeTime), linting, and formal verification
Timing and Constraints: In-depth knowledge of timing constraints (SDC) and experience achieving timing closure in advanced technology nodes
Scripting: Proficiency in scripting languages such as Tcl or Python for design automation
Preferred
Experience with high-speed digital design, SerDes, or optical interconnects
Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques
Familiarity with low-power design techniques and methodologies
Experience with UVM-based verification environments
Knowledge of photonics or mixed-signal IC design concepts
Company
Avicena Tech
Avicena Tech manufactures ultra-dense, ultra-low power petabit per second optical chip interconnects.
11-50 employees
H1B Sponsorship
Avicena Tech has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (1)
2023 (1)
Funding
Current Stage
Growth StageTotal Funding
$97.96MKey Investors
Tiger Global ManagementNational Science Foundation
2025-05-14Series B· $65M
2022-08-02Series A· $25M
2021-02-01Grant· $0.26M
Leadership Team
Bardia Pezeshki
Founder, CEO, CTO
Chris Pfistner
VP, Sales & Marketing
Recent News
Morningstar.com
2025-09-29
Crunchbase News
2025-05-16
Google Patent
2025-05-04
Company data provided by crunchbase