Avicena Tech · 3 months ago
ASIC Design Verification Engineer
Sunnyvale, CA
Full-time
Onsite
Mid Level
3+ years expAvicena Tech is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. They are seeking an ASIC Design Verification Engineer to ensure the functional correctness and performance of high-speed, low-power digital integrated circuits for silicon photonics and optical interconnect solutions.
ElectronicsIndustrial ManufacturingManufacturingSemiconductor
Responsibilities
Testbench Development: Develop comprehensive and reusable verification environments (Testbenches) from scratch using advanced methodologies like UVM (Universal Verification Methodology)
Verification Planning: Work closely with the architecture and design teams to define and execute thorough verification plans, including feature lists, test strategies, and coverage goals
Test Case Creation: Develop constrained-random, directed, and stress tests, as well as necessary sequences, scores, and functional coverage models
Functional Debugging: Execute simulations, analyze results, and effectively debug complex functional failures, working with design engineers to identify and resolve root causes
Coverage Closure: Drive functional and code coverage closure, identifying coverage holes and implementing targeted tests to achieve tape-out quality
Regression Management: Maintain and manage regression suites, optimizing simulation speed and efficiency
Formal Verification: Utilize formal verification techniques to prove correctness for critical design properties, such as clock domain crossing (CDC) and complex state machines
Scripting and Automation: Develop and maintain automation scripts (e.g., in Python or Perl) to enhance the verification flow and improve efficiency
Qualification
Required
Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
Experience: 3+ years of professional experience in ASIC/SoC design verification
UVM Expertise: Strong proficiency and hands-on experience in building and deploying reusable verification environments using SystemVerilog and UVM
Verification Languages: Expertise in SystemVerilog, and knowledge of scripting languages like Python or Perl
Tool Proficiency: Experience with industry-standard EDA simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)
Coverage Driven Methodology: Solid understanding of constrained-random verification and functional/code coverage analysis
Debugging Skills: Excellent analytical and problem-solving skills with a proven ability to debug complex digital logic and verification environments
Preferred
Experience verifying high-speed interfaces, SerDes, or communication protocols like Ethernet and PCIe
Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques
Knowledge of formal verification tools (e.g., Synopsys VC Formal, Cadence JasperGold)
Familiarity with low-power verification techniques
Experience with hardware description languages (HDL) like Verilog/SystemVerilog for basic design understanding
Exposure to physical layer (PHY) or mixed-signal verification concepts
Company
Avicena Tech
Avicena Tech manufactures ultra-dense, ultra-low power petabit per second optical chip interconnects.
11-50 employees
H1B Sponsorship
Avicena Tech has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (1)
2023 (1)
Funding
Current Stage
Growth StageTotal Funding
$97.96MKey Investors
Tiger Global ManagementNational Science Foundation
2025-05-14Series B· $65M
2022-08-02Series A· $25M
2021-02-01Grant· $0.26M
Leadership Team
Bardia Pezeshki
Founder, CEO, CTO
Chris Pfistner
VP, Sales & Marketing
Recent News
Morningstar.com
2025-09-29
Crunchbase News
2025-05-16
Google Patent
2025-05-04
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