Hewlett Packard Enterprise · 3 months ago
ASIC Engineer Sr Staff
San Jose, California, United States of America
Full-time
Hybrid
Senior Level, Lead/Staff
$148K/yr - $340K/yr
10+ years expHewlett Packard Enterprise is a global edge-to-cloud company that advances the way people live and work. They are seeking a seasoned Design-for-Test (DFT) Engineer to ensure the testability and reliability of high-speed ASICs, collaborating closely with various design teams to implement robust DFT solutions.
Data CenterEnterprise SoftwareInformation TechnologyIT ManagementNetwork Security
Responsibilities
Define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond
Collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features
Develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models
Analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations
Apply test constraints and perform STA analysis to ensure timing closure in test modes
Support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF)
Conduct silicon failure analysis and contribute to system-level debug and yield improvement
Automate DFT flows and analysis using scripting languages such as Perl and Tcl
Qualification
Required
10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains
Deep understanding of fault models: stuck-at, transition, path-delay
Expertise in scan compression, ATPG, and MBIST architecture
Experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair
Proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler
Simulation experience with Synopsys VCS and Cadence NC-Verilog
Timing analysis using PrimeTime and Cadence Tempus
Able to define test constraints and review STA reports to ensure timing closure in test modes
Debugging with waveform tools such as Novas and SimVision
Familiarity with ATE pattern formats (STIL, WGL) and JTAG SVF
Strong scripting skills in Perl and Tcl for automation and analysis
Preferred
Experience in silicon bring-up and system-level failure analysis for advanced process nodes (3nm and below)
Familiarity with high-speed networking protocols and system-level test strategies
Exposure to yield analysis and production test optimization
Benefits
Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion
Company
Hewlett Packard Enterprise
Hewlett Packard Enterprise is an edge-to-cloud company that uses comprehensive solutions to accelerate business outcomes.
10001+ employees
H1B Sponsorship
Hewlett Packard Enterprise has a track record of offering H1B sponsorships. Please note that this does not
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2025 (532)
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Funding
Current Stage
Public CompanyTotal Funding
$2.85BKey Investors
Elliott Management Corp.
2025-04-15Post Ipo Equity· $1.5B
2024-09-10Post Ipo Equity· $1.35B
2015-11-02IPO
Leadership Team
Antonio Neri
President & CEO
Fidelma Russo
EVP & GM, Hybrid Cloud and Chief Technology Officer
Recent News
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