Microchip ยท 2 months ago
Senior Technical Staff Engineer - Design for Test
N First St, San Jose, CA, USA
Full-time
Onsite
Senior Level, Lead/Staff
$88K/yr - $232K/yr
15+ years expMicrochip Technology, Inc. is a leading company in the semiconductor industry, known for its innovative technology and strong commitment to employee development. The Senior Technical Staff Engineer - Design for Test will collaborate with various teams to ensure effective testability features in FPGA and ASIC SOC, manage DFT requirements, and support the development of test patterns and validation processes.
ElectronicsManufacturingSemiconductor
Responsibilities
Manage DFT requirements across architecture, design, and product teams to ensure coverage, die cost, test cost and DFT integration requirements are met at the block and full chip level. Define, implement and validate DFT features at the FPGA full chip and sub-systems level
Collaborate closely with cross functional teams to support DFT insertion, synthesis, scan insertion, place-and-route, static timing analysis, timing closure, power analysis during test and quantifying full chip test coverage
Establish and maintain DFT design and insertion guidelines and documents best practices for all development teams to follow
Be current with emerging technologies and methodologies in DFT and incorporate them into the FPGA to continuously improve test cost and quality
Work with Test and Product engineers to support development of firmware targeted test patterns, ATPG and mBIST test feature validation processes, and silicon debug activities
Communicate project status and progress to chip lead and engineering management
Qualification
Required
15+ years of DFT engineering experience through DFT pre and post silicon cycles
Experience in creating and implementing complex FPGA/SoC DFT architecture in advanced technology nodes
Expert level knowledge about IJTAG and JTAG test access, Streaming Scan Network (SSN), scan compression and insertion, SAF/TDF/PDF ATPG, memory BIST and repair, logic BIST, MISRs, at-speed testing of SoC/FPGA, fault simulation, quantifying full chip test coverage, DFT mode timing constraints and power control during test
Familiar with DFT verification, silicon debug, memory and scan diagnostics
Experience in PHY, high-speed IO, digital communication and functional test development
Good understanding of Verilog, synthesis, physical implementation and STA
Good understanding of verification methodology
Preferred
Knowledge of FPGA design flow is a plus
Knowledge of embedded design and firmware methodology is a plus
Understanding Arm or RISC IP's, high speed interfaces such as PAM4 SerDes, DDR4/5, etc. is a plus
Experience in leading multiple FPGA/SoC projects
Benefits
Health benefits that begin day one
Retirement savings plans
Industry leading ESPP program with a 2 year look back feature
Company
Microchip
10001+ employees
H1B Sponsorship
Microchip has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (170)
2024 (113)
2023 (116)
2022 (119)
2021 (94)
2020 (100)
Funding
Current Stage
Late StageTotal Funding
unknown2014-02-10Acquired
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