Qualcomm · 2 months ago
HW SOC/ASIC Physical Design Engineer, Senior
San Diego, California, United States of America
Full-time
Onsite
Mid, Senior Level
$116K/yr - $173K/yr
3+ years expQualcomm Technologies, Inc. is seeking a highly skilled and motivated Physical Design Engineer to join their team. The ideal candidate will have hands-on experience in RTL-to-GDSII flow, focusing on architecting and implementing robust, low-skew, power-efficient clock distribution networks.
Artificial Intelligence (AI)Generative AISoftwareTelecommunicationsWireless
Responsibilities
Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry-standard tools (e.g., Innovus, ICC2)
Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime)
Collaborate with RTL designers to resolve timing, congestion, and DRC issues
Optimize design for power, performance, and area (PPA)
Conduct formal equivalence checks between RTL and netlist
Support physical verification including DRC, LVS, and antenna checks
Work closely with backend teams for tapeout preparation and signoff
Excellent scripting skills (TCL, Python, Perl) for reference flow automation
Execute full-chip and block-level physical verification including DRC, LVS, ERC, antenna, and density checks using industry-standard tools (e.g., Calibre, Pegasus, ICV)
Customize and optimize reference physical verification flows to align with project needs and foundry requirements
Perform GDS-to-GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness
Debug and resolve physical verification violations, working closely with layout, design, and CAD teams
Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists
Support signoff verification, including multi-corner/multi-mode analysis and ECO validation
Develop and maintain automation scripts for verification flows, reporting, and regression testing
Interface with EDA vendors to resolve tool issues and improve flow robustness
Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability
Ensure timely delivery of clean GDSII for tapeout, with full verification signoff
Perform full-chip and block-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus)
Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners
Collaborate with RTL, synthesis, and physical design teams to ensure timing-aware design practices
Debug and resolve setup, hold, and transition violations across various PVT corners
Drive timing closure through iterative optimization and ECO implementation
Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability
Analyze clock tree timing, including skew, latency, and jitter impacts
Support signoff timing verification, including cross-domain timing and false/multicycle path handling
Interface with EDA vendors to resolve tool issues and improve flow robustness
Participate in design reviews, providing insights on timing risks and mitigation strategies
Define and implement low-power architecture using CLP methodology across RTL and physical design stages
Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications
Customize and optimize low-power reference flows to meet project-specific requirements
Collaborate with RTL, synthesis, and physical design teams to integrate power-aware features such as power gating, retention, isolation, and level shifting
Perform power-aware static checks, simulation, and formal verification to validate power intent
Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing
Support signoff verification including power-aware LVS/DRC, STA, and EM/IR analysis
Interface with EDA vendors to resolve tool issues and improve low-power flow robustness
Participate in design reviews, providing insights on power architecture, risks, and mitigation strategies
Ensure compliance with foundry low-power guidelines and contribute to successful tapeout
Qualification
Required
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience
PhD in Science, Engineering, or related field
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
3+ years of experience in physical design, with a focus on clock tree design and implementation
Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design
Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime)
Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies
Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis
Familiarity with low-power design techniques, including clock gating and multi-voltage domains
Preferred
Experience with custom clock tree architectures such as H-tree, mesh, or spine-based topologies
Knowledge of EM/IR analysis, thermal-aware clocking, and reliability modeling
Exposure to high-speed interface clocking (e.g., SerDes, DDR, PCIe)
Understanding of package-level clock planning and signal integrity
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
10001+ employees
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
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Trends of Total Sponsorships
2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
Leadership Team
Cristiano Amon
President and Chief Executive Officer
I
Isaac Eteminan
CEO
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