AMD ยท 2 months ago
STA ASIC Design Engineer
San Jose, California
Full-time
Hybrid
Mid LevelAMD is a company that focuses on building innovative products for next-generation computing experiences. They are seeking an STA ASIC Design Engineer to contribute to the development of large SoCs by building and verifying timing constraints for intricate designs.
AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor
Responsibilities
Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency
Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks
Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows
Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts)
Qualification
Required
Extensive experience in SDC development and debugging
Familiar with enhancing various RTL quality metrics for complex, hierarchical designs
Ability to automate processes for increased efficiency
Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes
Strong written and verbal communication skills
Structured, well-organized work habits
Team and goal oriented
Development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
Lead the effort to maintain RTL quality metrics in complex, hierarchical designs
Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues
Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) workflows
Blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities in both EDA environment and standalone Linux Tcl shell scripts
Bachelors or Masters degree in computer engineering/Electrical Engineering
Preferred
Worked with EDA tools that enable RTL quality checks
Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows
Experience with analyzing the timing reports and identifying both the design and constraints related issues
Ability to multitask, grasp new flows/tools/ideas
Experience in improving the methodologies
Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc
Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT)
Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters
Strong analytical and problem-solving skills
Benefits
Benefits offered are described: AMD benefits at a glance
Company
AMD
Advanced Micro Devices is a semiconductor company that designs and develops graphics units, processors, and media solutions.
Founded in 1969
10001+ employees
H1B Sponsorship
AMD has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (836)
2024 (770)
2023 (551)
2022 (739)
2021 (519)
2020 (547)
Funding
Current Stage
Public CompanyTotal Funding
unknownKey Investors
OpenAIDaniel Loeb
2025-10-06Post Ipo Equity
2023-03-02Post Ipo Equity
2021-06-29Post Ipo Equity
Leadership Team
Lisa Su
Chair & CEO
Mark Papermaster
CTO and EVP
Recent News
2026-01-13
Morningstar.com
2026-01-11
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