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SpaceX · 2 weeks ago

Sr. SOC/ASIC DFT Engineer (Silicon Engineering)

Bastrop, TX

Full-time

Onsite

Senior Level

5+ years exp

SpaceX is actively developing technologies to enable human life on Mars and is seeking a motivated engineer to work on next-generation ASICs for their Starlink project. The role involves developing DFT architectures and collaborating with cross-disciplinary teams to expand the performance of the Starlink network.

Advanced MaterialsAerospaceManufacturingNational SecuritySpace Travel

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools

Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems

Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows

Run and debug non-timing and SDF annotated gate-level simulations

Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization

Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++

Qualification

DFT engineeringSiemens Tessent toolsAutomated Test EquipmentPost-silicon validationPythonProblem-solvingCommunication skillsCollaboration

Required

Bachelor's degree in electrical engineering, computer engineering, or physics

5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing

Preferred

Master's or PhD in electrical engineering, computer engineering, physics, or related engineering field

Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs

Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug

Experience collaborating with cross-functional teams (e.g., design, verification, and manufacturing) to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows

Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low-power DFT techniques using Siemens Tessent

Experience with In-System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics, preferably using Siemens Tessent tools

Hands-on experience with Tessent Streaming Scan Network

Experience with cell-aware fault models in ATPG

Excellent problem-solving skills, with the ability to analyze complex test failures and implement corrective actions

Strong communication skills for documenting test strategies, reporting results, and presenting to stakeholders

Ability to work in a fast-paced environment, handling multiple projects and adapting to evolving technology nodes (e.g., 7nm and below)