Marvell Technology · 2 months ago
Analog IC Design Engineer, Principal Engineer
Santa Clara, CA
Full-time
Onsite
Lead/Staff
$166K/yr - $248K/yr
10+ years expMarvell Technology is a leading provider of semiconductor solutions that power data infrastructure. They are seeking a Principal Analog IC Designer to lead a team in designing sophisticated CMOS transceiver products, focusing on performance targets and design verification.
DSPInternet of ThingsManufacturingSemiconductorWireless
No H1B
U.S. Citizen Only
Responsibilities
Seeking a Principal Analog IC Designer to be part of a Marvell's central engineering team designing highly sophisticated CMOS transceiver/SERDES/PLL products
Responsibilities would span architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc
In this role, successful candidate will lead a team of analog design engineers, interface with layout, verification, and application teams and manage delivery of analog IP to successfully bring designs from concept to production
Qualification
Required
Master's degree and/or PhD in Electrical Engineering or related fields
10+ years of experience in analog IC design
Experience in PLL, Data Converters, Oscillators and high-speed SerDes design including Receiver and Transmitter design
Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools)
Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution
Good understanding of analog layouts in FinFet and its effect on high-speed designs
Experienced in system level pre-tape out analog validation
Experienced in lab chip bring-up and debugging efforts
Strong communication skills
Preferred
Experience with design D2D interface such as UCIe
Experience with 112G+ SerDes speed, especially short reach and low power designs
Experience in Single-ended High Density Parallel Interface for Chip to Chip Communication, DDR5/LPDDR5; GDDR6/LPDDR6
Benefits
Flexible time off
401k
Year-end shutdown
Floating holidays
Paid time off to volunteer
Company
Marvell Technology
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology.
5001-10000 employees
Funding
Current Stage
Public CompanyTotal Funding
unknown2017-01-20Post Ipo Equity
2016-05-13Post Ipo Equity
2015-02-05Acquired
Leadership Team
Matthew Murphy
Chairman and CEO
Radha Nagarajan
SVP & CTO, Optical Engineering
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