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Tenstorrent · 3 days ago

RISC-V CPU Microarchitecture / RTL

United States

Full-time

Remote

Entry, Mid, Senior Level

$100K/yr - $500K/yr

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. The RISC-V CPU RTL owner will play a key role in developing next-generation CPU design, requiring a deep understanding of CPU design including Architecture, RTL, Design Verification, and Physical Design Flow.

AI InfrastructureApplication Specific Integrated Circuit (ASIC)Artificial Intelligence (AI)ElectronicsMachine LearningSemiconductor

Comp. & Benefits

No H1B

U.S. Citizen Only

Responsibilities

RISC-V CPU Unit Microarchitecture Specification: Define and develop microarchitecture specifications for the assigned unit (branch predictor, rename, instruction scheduling, vector execution, load/store, vector load/store support). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure

RISC-V CPU Core Unit RTL Design: The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA

AI Assisted Design Adaption: To maximize the team’s output, the candidate actively uses AI tools to accelerate the CPU design process

Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor junior members in the team

Qualification

CPU RTL DesignDesign VerificationCPU MicroarchitectureRISC-V ArchitectureHardware Description LanguagesProblem-solvingCommunication SkillsTeam Collaboration