Chip Interfaces, through its JESD204C IP, supports Extoll's collaboration with Eridan

SerDes IP for low power telecoms chip

Senior Digital / RTL Design Engineer

EXTOLL GmbH is a leader in state-of-the-art High-Speed Serializer-Deserializer (SerDes) IP and interconnect technologies for semiconductor chips. The Senior Digital / RTL Design Engineer will be part of the system design team, responsible for delivering high quality and performing results for various network solutions and protocols, from specification to implemented netlist.

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