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Advanced Microdevices Pvt. Ltd. (India) · 2 months ago

Infinity Fabric Verification Engineer

Austin, TX

Full-time

Hybrid

Senior Level

7+ years exp

Advanced Micro Devices, Inc is dedicated to building innovative products that enhance computing experiences across various domains including AI and data centers. They are seeking an Infinity Fabric Verification Engineer to verify configurable switches and die-to-die interconnects, working closely with design and verification teams to develop and execute test plans in a metric-focused environment.

BiopharmaBiotechnologyIndustrialManufacturing

Responsibilities

Develop and enhance SystemVerilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects

Develop and enhance BFM/UVC for industry-wide and AMD internal protocols

Collaborate with architects, hardware engineers and multiple IP development groups

Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture

Mentor junior engineers

Qualification

SystemVerilogUVMVerification environmentsC++Object-Oriented ProgrammingScriptingRTL designFormal verificationMentoringCollaboration

Required

Proven experience verifying complex design blocks at the IP or SoC level using SystemVerilog/UVM or related technologies

Comfortable creating and executing on testplans in collaboration with design and verification colleagues in a metric-focused environment

Develop and enhance SystemVerilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects

Develop and enhance BFM/UVC for industry-wide and AMD internal protocols

Collaborate with architects, hardware engineers and multiple IP development groups

Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture

Mentor junior engineers

BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science

Preferred

Architected and developed complex verification environments in SystemVerilog or C++ and infrastructure, including scripting using Perl, Ruby, Make, or the likes

Experience in developing or refactoring testbench, UVC, or BFM code using Object-Oriented Programming (OOP) principles

Exposure to RTL design, software development, formal verification, or other related domains

7-12 years industry experience is preferred