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BAE Systems, Inc. · 2 weeks ago

Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)

Nashua, NH

Full-time

Onsite

Senior Level, Lead/Staff

$130K/yr - $222K/yr

8+ years exp

BAE Systems, Inc. is an international defense, aerospace, and security company focused on delivering advanced electronics and information technology solutions. They are seeking experienced senior level FPGA Design Verification Engineers to lead teams, mentor junior engineers, and develop verification environments for advanced electronic systems used in Electronic Warfare. The role involves planning, architecting, and developing configurable testbenches, as well as enhancing the company's verification processes.

Defense & Space

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Plan, architect, develop, and use configurable, self-checking testbenches implemented in SystemVerilog/UVM and/or VHDL

Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functions in Electronic Warfare systems

Collect and analyze coverage metrics, then use that information to improve the effectiveness of testcases

Enhance your leadership skills while leading small to medium sized DV teams

Create reusable Verification IP to be shared across the organization

Drive changes to our process and methodologies

Enhance your DV skills as well as your knowledge of Electronic Warfare while working with subject matter experts

Mentor junior engineers across multiple U.S. locations

Qualification

SystemVerilog/UVMFPGA/ASIC designTest plans developmentDigital Signal ProcessingFPGA Design ExperienceMentoring skillsPerl/PythonC++/JavaGit/Jira/BitBucketMatlab/SimulinkReusable Verification IP

Required

Bachelor's Degree and 8+ years work experience (or equivalent experience)

Current Security Clearance (Secret), or eligible to obtain one

Experience planning, architecting, developing, and using constrained random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL

Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence)

Proven track record of managing and executing to schedules, and driving tasks to closure. Candidates should also be comfortable multitasking because they may be asked to support multiple projects

Strong communication and documentation skills

Experience developing and implementing test plans

Ability to work effectively in a multi-site or borderless environment