Qualcomm · 2 hours ago
Physical Design Engineer - Multiple Levels
Santa Clara, CA
Full-time
Onsite
Entry, Mid, Senior Level
$140K/yr - $230K/yr
2+ years expQualcomm Technologies, Inc. is a leading technology innovator that drives communication and data processing transformation for a smarter, connected future. They are seeking candidates for physical design engineering positions in their SOC and core design team, where the engineer will innovate and implement chips and cores using state-of-the-art tools and technologies.
Artificial Intelligence (AI)Generative AISoftwareTelecommunicationsWireless
Responsibilities
Innovate, develop, and implement chips and cores using state-of-the-art tools and technologies
Responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU, Camera and other MM, DDR, Modem, Audio
Development and enablement of low power implementation methods
Customized P&R to achieve area reduction, performance, and power goals
Good understanding of functional and test (DFT) mode constraints for place and route
Floorplanning
Power planning
IR drop analysis
Cell placement
Multi-mode & multi-corner (MMMC) clock tree synthesis
Routing
Timing optimization and closure
RC extraction
Signal integrity
Cross talk noise and delay analysis
Debugging timing violations for MMMC designs
Implementing timing fixes and functional ECOs
Debugging and fixing physical violations
Formal verification
Design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product
Qualification
Required
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience
OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience
OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
2 -10+ years industry experience in Physical Design
Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler
Timing closure experience in Synopsys PTSI
Formal verification experience
Power domain analysis experience
Physical verification experience
Good understanding of functional and test (DFT) mode constraints for place and route
Floorplanning, power planning, IR drop analysis, cell placement
Multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure
RC extraction, signal integrity, cross talk noise and delay analysis
Debugging timing violations for MMMC designs, implementing timing fixes and functional ECOs
Debugging and fixing physical violations, and formal verification
Deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell and C
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
10001+ employees
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
Leadership Team
Cristiano Amon
President & CEO
I
Isaac Eteminan
CEO
Recent News
2026-01-17
Company data provided by crunchbase