Senior Staff Engineer, Serdes Layout Design jobs in United States
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Samsung Semiconductor · 7 hours ago

Senior Staff Engineer, Serdes Layout Design

Samsung Semiconductor is a global leader in Memory, System, LSI, and LCD technologies, contributing to advancements in 5G, SOC, memory, and display. The role of Senior Staff Engineer involves working closely with circuit designers to optimize high-speed mixed-signal layout tasks and enhance the performance of SERDES analog PHY.

Semiconductor
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H1B Sponsor Likelynote
Hiring Manager
Vu LeDang
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Responsibilities

Working with remote circuit designers to determine the chip floorplan. You need to come up with strategies to optimize the parasites, reduce area, and improve High Speed SERDES/analog performance
You need to be able to estimate schedule and come up with plan how to get things done within a dedicated time frame
You should be able to read the design document provided by the foundry and figure out how to resolve issues like latch-up and DRC
Perform custom layout using Virtuoso, and be able to get LVS/DRC clean
You should be familiar with CAD tools, including Virtuoso, Calibre LVS, DRC, SkillCad and so on
Desired to have experience on chip level design, like bump, pad, and ESD strategies
Good communication skills to discuss with circuit designer

Qualification

High Speed SERDES layoutSub-micron CMOS technologiesCAD tools proficiencyCalibre LVS/DRCProgramming in SKILLPerlPythonAnalog/mixed-signal layoutCuriosityResilienceCreativeCommunication skillsProject leadershipCollaborationInnovative

Required

Bachelors with 15+ years, Masters with 13+ years or PhDs with 10+ years of experience
Experience in RF/analog/mixed-signal/serdes layout design of deep submicron CMOS circuits and recent experience on advance nodes including FinFET and GAA technologies
High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, reports
Familiar with analog/mixed-signal related circuit layout, including high-speed I/O block such as comparator/transmitter/receiver/PLLs and so on
Experience with CADENCE or MENTOR GRAPHICS layout tools
Good communication skills with design leads as well as engineers for schedule planning
You're inclusive, adapting your style to the situation and diverse global norms of our people
An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding
You're collaborative, building relationships, humbly offering support and openly welcoming approaches
Innovative and creative, you proactively explore new ideas and adapt quickly to change
You should have experiences doing layout with sub-micron CMOS technologies
You'll work with designers to optimize the performance and power consumption of SERDES analog PHY
Working with remote circuit designers to determine the chip floorplan. You need to come up with strategies to optimize the parasites, reduce area, and improve High Speed SERDES/analog performance
You need to be able to estimate schedule and come up with plan how to get things done within a dedicated time frame
You should be able to read the design document provided by the foundry and figure out how to resolve issues like latch-up and DRC
Perform custom layout using Virtuoso, and be able to get LVS/DRC clean
You should be familiar with CAD tools, including Virtuoso, Calibre LVS, DRC, SkillCad and so on

Preferred

Experience of leading a complicated layout project, and tape-out successfully
Programming knowledge in SKILL, Perl, and/or Python is a bonus

Benefits

Medical/Dental/Vision/401k
Charitable giving match
4+ weeks of paid time off a year
Holidays and sick leave
Stipend for fertility care or adoption
Medical travel support
Virtual vet care for your fur babies
On-demand apps and free confidential therapy sessions
Onsite Café and gym
Virtual classes
Flexible environment

Company

Samsung Semiconductor

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Samsung Semiconductor, Inc. (SSI) is a multi-billion dollar wide range of industry-leading semiconductor solutions.

H1B Sponsorship

Samsung Semiconductor has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (130)
2024 (110)
2023 (153)
2022 (134)
2021 (124)
2020 (134)

Funding

Current Stage
Late Stage

Leadership Team

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Daehee Lee
Principal Engineer
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Eric Hibbard
Director, Product Planning – Storage Networking & Security
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Company data provided by crunchbase