d-Matrix · 2 months ago
Test Engineer ATE - Contract
Santa Clara
Contract
Hybrid
Senior Level, Lead/Staff
$100/hr - $125/hr
8+ years expd-Matrix is focused on unleashing the potential of generative AI to power the transformation of technology. They are seeking an ATE Test Engineer to develop and oversee SoC test strategies, interact with manufacturing partners, and implement ATE programs from design through high volume production ramp.
AI InfrastructureArtificial Intelligence (AI)Cloud InfrastructureData CenterSemiconductor
Responsibilities
Develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp
Collaboration with design DFT team to define test strategy, create and own test plan
Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality
Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – AC/DC SCAN, MBIST, DBIst, DSerDes, DDR, D2D, DIMC and other functional tests
Strong knowledge of lot genealogy from 2DiD bar code down to ECID in eFuse for device serial number, chiplet Id and die information
Expertise in production test of high speed SerDes operating at 16Gbps and higher
Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug
Experience with lab equipment including protocol analyzers and oscilloscopes
Experience with data conversion between STDF file format into csv file format using scripts including extracting ECID reside with eFuse block
Proficiency in modern programming languages such as C/C++, Python
Qualification
Required
Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Master's is preferred
8-year experience releasing complex SoC/silicon products to high volume manufacturing
Working knowledge of high-speed protocols like PCIe, LPDDRx, HBM, etc
Professional attitude with ability to execute on multiple tasks with minimal supervision
Strong team player with good communication skills to work alongside a team of high caliber engineers
Entrepreneurial, open-mind behavior and can-do attitude
Hands-on experience with high-speed SoC test program/hardware development on Advantest 93k test platform
Collaboration with design DFT team to define test strategy, create and own test plan
Familiar with high-speed and high power load board design techniques
Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality
Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – AC/DC SCAN, MBIST, DBIst, DSerDes, DDR, D2D, DIMC and other functional tests
Strong knowledge of lot genealogy from 2DiD bar code down to ECID in eFuse for device serial number, chiplet Id and die information
Expertise in production test of high speed SerDes operating at 16Gbps and higher
Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug
Experience with lab equipment including protocol analyzers and oscilloscopes
Experience with data conversion between STDF file format into csv file format using scripts including extracting ECID reside with eFuse block
Proficiency in modern programming languages such as C/C++, Python
Preferred
Fluent in data processing using high level programming languages
Experience in running internal loopback at wafer sort as well as at FT
Familiarity database setup using JMP as YMS (Yield Management Tool)
Company
d-Matrix
D-Matrix is a platform that enables data centers to handle large-scale generative AI inference with high throughput and low latency.
51-200 employees
H1B Sponsorship
d-Matrix has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (20)
2024 (15)
2023 (8)
2022 (7)
Funding
Current Stage
Growth StageTotal Funding
$429MKey Investors
Temasek HoldingsTSVC
2025-11-12Series C· $275M
2023-09-06Series B· $110M
2022-04-20Series A· $44M
Leadership Team
Peter Buckingham
Senior Vice President, Software Engineering
Recent News
2025-12-22
2025-12-17
Crunchbase News
2025-12-10
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