Tenstorrent · 2 months ago
SoC Physical Design Verification Engineer
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. They are seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure high-quality silicon across advanced technology nodes.
AI InfrastructureApplication Specific Integrated Circuit (ASIC)Artificial Intelligence (AI)ElectronicsMachine LearningSemiconductor
Responsibilities
Drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes
Lead physical verification closure (DRC, LVS, ERC, etc.)
Debug issues using standard industry PV tools
Collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts
Qualification
Required
BS or MS in Engineering (Electrical, Electronics, or related field)
7–14 years of hands-on experience in CPU/IP/SoC physical verification
Strong command of industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.)
Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification
Solid understanding of advanced node challenges (7nm, 5nm, 3nm) and FinFET design considerations
Scripting proficiency (Python, TCL) for automation and flow optimization
Familiarity with ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM)
Benefits
Highly competitive compensation package and benefits
Company
Tenstorrent
Tenstorrent develops AI hardware and software solutions for data processing and machine learning application.
Funding
Current Stage
Late StageTotal Funding
$1.03BKey Investors
FidelityEPIQ Capital GroupEclipse Ventures
2024-12-02Series D· $693M
2023-08-02Series Unknown· $100M
2021-05-20Series C· $200M
Recent News
2026-01-07
TechRadar.com
2026-01-07
2026-01-06
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