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Meta · 2 months ago

Research Scientist Intern, Silicon Performance Architecture (PhD)

Austin, TX

Internship

Onsite

Intern

$7,313/mo - $12,134/mo

Meta builds technologies that help people connect, find communities, and grow businesses. They are seeking a Research Scientist Intern to improve performance modeling collateral and guide the architecture of AR/MR silicon through various performance explorations and optimizations.

Computer Software

Comp. & Benefits

Responsibilities

Build APIs and/or custom wrappers to integrate various perf modeling components, develop test suites to formally verify the functionality and performance of the integrated models

Identify areas of optimization to increase the speed of simulation infrastructure either through code refactoring or code restructuring

Conduct performance & power explorations of various architectural components using built performance models (including blocks such as NoC, DRAM, MMUs, etc)

Qualification

Performance ModelingComputer ArchitectureC/C++ ProgrammingPython ScriptingPerformance SimulationHeterogeneous HardwarePower Performance Trade-offsCross-functional CommunicationAcademic PublicationTeam EnvironmentSimulation Tools

Required

Currently has, or is in the process of obtaining, a PhD in Computer Science, Electrical Engineering or related field

Experience with programming in C/C++ and Python (scripting)

Experience in computer architecture (NoC, DRAM, Cache, MMU)

Understanding of how to leverage performance modeling to support architectural exploration, with exposure to heterogeneous hardware architectures

Understanding of HW power, performance and area trade offs

Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment

Preferred

Experience working and communicating cross functionally in a team environment

Intent to return to degree-program after the completion of the internship/co-op

Experience in academic computer architecture simulators such as GEM5, SIMICS, etc

Publication track record in computer architecture conferences is a plus - covering areas in high performance computing, memory systems, multi-core and/or accelerator architectures (e.g., ISCA, ASPLOS, MICRO, HPCA, DAC, NOCS, ISPASS, PACT, etc.)