Intel Corporation · 2 months ago
High-Speed I/O PHY Architect
US, California, Folsom
Full-time
Onsite
Senior Level, Lead/Staff
$215K/yr - $350K/yr
12+ years expIntel Corporation is a leading technology company seeking a High-Speed I/O PHY Architect to drive innovation in high-speed PHY architecture for next-generation client SoCs. In this role, you will lead architectural definition, conduct IP evaluations, and mentor junior engineers while collaborating with cross-functional teams to enhance product performance and efficiency.
Semiconductors
Responsibilities
Architectural Leadership: Lead the architectural definition and integration of high-speed PHYs for client SoCs, including PCIe, CXL, USBx (e.g., eUSB2, USB3, USB4), Display, MIPI (D-PHY, C-PHY, M-PHY), Ethernet, and TSN. Collaborate with platform and product architects to analyze requirements and define critical performance, power, and area specifications to ensure the success of our products
IP Evaluation: Conduct technical evaluations of both internal and external PHY IPs, analyzing their performance characteristics against product requirements, and ensuring strategic alignment with overall product goals. Define detailed IP requirements, lead vendor engagement, and make strategic IP selection recommendations based on technical feasibility, cost-effectiveness, and long-term roadmap alignment
Technology Vision: Proactively research and evaluate emerging high-speed I/O technologies, industry trends, and evolving standards. Identify and champion opportunities to incorporate these advancements into our product roadmap, enhancing performance, power efficiency, and feature sets, and positioning our products for competitive advantage
Technical Documentation: Create clear and comprehensive architecture specifications and rigorous integration guidelines. Provide review and constructive feedback on related architectural specifications to ensure alignment with overall SoC goals
Technical Mentorship and Collaboration: Provide technical guidance and mentoring to junior engineers, fostering their growth and contributing to the overall team expertise. Champion a collaborative environment across multiple teams
Post-Silicon Leadership: Serve as a technical lead in the post-silicon debug and validation of high-speed I/O interfaces, leading taskforces and driving the resolution of complex issues. Oversee the validation process to ensure seamless and high-quality implementations
Qualification
Required
BS degree in Electrical/Computer Engineering with a minimum of 15 years of experience
Master's or PhD degree in Electrical/Computer Engineering with minimum 12 years of experience
Preferred
High familiarity with industry trends within the HSIO domain and the ability to map them to Intel roadmap/products and segment strategies
Prior hands-on experience in High-Speed IO PHY Architecture and Design
Strong knowledge in the interoperability of HSIO PHYs within the PCIe, SATA, Ethernet, USB2, USB3, USB4, Display or MIPI IO Controller subsystems
Strong technical leadership and communication skills
Benefits
Competitive pay
Stock
Bonuses
Benefit programs which include health, retirement, and vacation
Company
Intel Corporation
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside.
10001+ employees
H1B Sponsorship
Intel Corporation has a track record of offering H1B sponsorships. Please note that this does not
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Funding
Current Stage
Late StageLeadership Team
Brea Watts, MFA
Communications Manager, CEO
Carol Bartz
CEO
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