Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer jobs in United States
cer-icon
Apply on Employer Site
company-logo

Arista Networks · 2 months ago

Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer

positionSanta Clara, CA, USA
timeFull-time
remoteOnsite
senioritySenior Level
money$150K/yr - $230K/yr
date7+ years exp

Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. They are seeking a Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer to lead the design, simulation, and validation of high-speed electrical interconnects and power delivery networks for next-generation optical modules and engines.

Cloud ComputingData Center AutomationHardwareInformation TechnologySoftware
check
Culture & Values
check
H1B Sponsor Likelynote

Responsibilities

Lead signal integrity (SI) and power integrity (PI) efforts for high-speed optical transceiver modules, high density optical interconnect platforms
Design and simulate high-speed channels up to 448G per lane (e.g., 224G/448G PAM4) across PCBs, packages, and connectors
Perform pre- and post-layout SI/PI simulations using tools like Ansys HFSS, Keysight ADS, Cadence Sigrity, and SiSoft QSI
Develop and validate PCB stackups, via structures, high-speed breakout regions, and connector transitions to meet compliance with IEEE, CEI, and MSA standards
Work closely with electrical, optical, and layout teams to define routing constraints, reference plane designs, and return path continuity for minimal signal degradation
Design and optimize PDNs to meet target impedance, minimize noise coupling, and support fast transient loads for high-speed DSPs and ICs
Provide SI/PI layout guidelines to PCB designers and review placement/routing for high-speed paths and power domains
Collaborate with validation teams to perform measurements (TDR, VNA, eye diagram, jitter, BER) and correlate with simulation models
Engage with ASIC, connector, and packaging vendors to support co-design and channel optimization across multiple integration layers
Drive root cause analysis of SI/PI-related issues during validation and production builds

Qualification

Signal Integrity (SI)Power Integrity (PI)High-speed interconnectsAnsys HFSS224G/448G PAM4 signalingPCB stackup designPower delivery designTDRVNA usageCross-functional communicationProblem-solving

Required

B.S. or higher in Electrical Engineering, Applied Physics, or a related discipline
7+ years of experience in SI/PI engineering for high-speed interconnects in optical or networking hardware
Proven experience with 112G, 224G, and 448G PAM4 signaling and related SI/PI challenges
Strong understanding of PCB stackup design, via modeling, impedance control, and crosstalk mitigation
Expertise in signal integrity simulation tools such as Ansys HFSS, Keysight ADS, Sigrity, or similar
Experience with power delivery design, including decoupling strategies, PDN impedance analysis, and noise mitigation techniques
Familiarity with transceiver MSA form factors (QSFP-DD, OSFP) and standards from IEEE, CEI, OIF
Hands-on experience using TDRs, VNAs, oscilloscopes, and other lab equipment to validate simulation results
Excellent problem-solving, documentation, and cross-functional communication skills

Preferred

M.S. or Ph.D. in Electrical Engineering or a related field with emphasis on high-speed or mixed-signal systems
Experience with co-packaged optics, chiplet-based architectures, or advanced substrate technologies
Familiarity with EMI/EMC considerations and signal/power isolation in densely integrated photonic-electronic systems
Understanding of thermal and mechanical effects on SI/PI performance and long-term reliability
Experience working with fabrication vendors, ASIC teams, and contract manufacturers to ensure end-to-end channel integrity

Benefits

Medical
Dental
Vision
Wellbeing
Tax savings
Income protection

Company

Arista Networks

twittertwittertwitter
Glassdoor4.1
company-logo
Arista Networks is a computer networking firm delivering cloud networking solutions for large data center and computer environments.
dateFounded in 2004
location
Santa Clara, California, USA
people-size1001-5000 employees
web-link
http://www.arista.com

H1B Sponsorship

Arista Networks has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (204)
2024 (144)
2023 (111)
2022 (147)
2021 (152)
2020 (120)

Funding

Current Stage
Public Company
Total Funding
$7.4M
Key Investors
Summit Partners
2015-05-27Post Ipo Debt· $2.62M
2014-06-06IPO
2013-12-21Series Unknown· $4.78M

Leadership Team

leader-logo
Jayshree Ullal
Chief Executive Officer and Chair
linkedin
leader-logo
Kenneth Duda
CTO and SVP Software Engineering
linkedin

Recent News

Fierce Network
Arista’s Ullal: Ethernet is the 'eventual winner' for AI networking
2026-01-09
Investing.com
US stock futures tick up as oil companies jump on Venezuela shock
2026-01-05
Trak.in - Indian Business of Tech, Mobile & Startups
This Indian Lady Beats Satya Nadella, Sunder Pichai To Become Richest Indian-Origin Business Leader
2026-01-03
Company data provided by crunchbase