Mythic · 2 months ago
Senior RTL Design Engineer
Palo Alto, CA
Full-time
Hybrid
Senior Level, Lead/Staff
$120K/yr - $225K/yr
8+ years expMythic is building the future of AI computing with breakthrough analog technology. They are seeking experienced RTL Design Engineers to design and implement components for their next-generation AI processors, focusing on high-performance and low-power logic.
AI InfrastructureArtificial Intelligence (AI)Computer VisionMachine LearningSemiconductorSoftware Engineering
Responsibilities
Design and implement RTL for Mythic's next-generation AI processor
Contribute to the development of a novel digital dataflow architecture, including a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines
Develop and optimize high-performance, low-power components such as datapaths, controllers, memory subsystems, and interconnects
Collaborate with architects and verification engineers to define microarchitecture and ensure functional correctness
Drive timing closure by working closely with synthesis and physical design teams
Participate in design reviews and contribute to improving RTL coding practices and methodologies
Qualification
Required
Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science
8+ years of industry experience in RTL design, microarchitecture, and architecture development
Solid understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies)
Hands-on experience with one or more of the following subsystems: scheduling fabrics, high-performance interconnects, DMA engines, memory controllers, or datapath/control logic
Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines
Familiarity with timing constraints, physical design considerations, and EDA flows
Hands-on experience with simulation, synthesis, linting, and static timing analysis tools
Strong problem-solving and communication skills with ability to work in cross-functional teams
Preferred
Familiarity with network-on-chip (NoC) architectures
Expertise in low-power design techniques (clock gating, power gating, multi-voltage domains)
Experience with timing closure in advanced technology nodes and collaboration with physical design teams
Strong skills in performance modeling and trade-off analysis (PPA optimization)
Hands-on experience with emulation/FPGA prototyping for early RTL validation
Familiarity with AI, DSP, or other parallel compute architectures
Strong scripting ability (Python or similar) for design automation and productivity
Company
Mythic
Mythic develops analog matrix processors and key cards based on analog compute-in-memory.
11-50 employees
H1B Sponsorship
Mythic has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2022 (7)
2021 (4)
2020 (6)
Funding
Current Stage
Growth StageTotal Funding
$289.65MKey Investors
DCVCValor Equity PartnersSBVA
2025-12-17Series Unknown· $125M
2023-03-09Series Unknown· $13M
2021-05-11Series C· $70M
Leadership Team
Dave Fick
CTO & Co-Founder
Recent News
alleywatch.com
2025-12-24
2025-12-24
Company data provided by crunchbase