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Tenstorrent · 1 day ago

Staff Engineer, IP Packaging and Methodology

United States

Full-time

Remote

Senior Level, Lead/Staff

$100K/yr - $500K/yr

5+ years exp

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. We are seeking an experienced IP Packaging and Methodology Engineer to join our RISC-V IP Engineering team, where you will architect automated packaging workflows and drive cross-functional process improvements for high-quality IP delivery.

AI InfrastructureApplication Specific Integrated Circuit (ASIC)Artificial Intelligence (AI)ElectronicsMachine LearningSemiconductor

Comp. & Benefits

No H1B

U.S. Citizen Only

Responsibilities

Design and implement automated IP packaging pipelines using Python, Bash, and GitLab CI/CD frameworks supporting IEEE 1735 encryption, IP-XACT, and ARM AMBA specifications

Establish automated validation gates: lint checking, simulation regression hooks, documentation completeness verification, and generate customer-facing deliverables (datasheets, integration guides, reference testbenches)

Analyze and architect scalable solutions for IP delivery workflows, defining best practices for documentation, configuration management, and quality assurance

Debug complex IP integration issues spanning RTL implementation, configuration management, timing constraints, and system-level integration; work within SystemVerilog verification environments

Drive cross-functional initiatives partnering with Design, Verification, Physical Design, Software, and Product Management to standardize IP interfaces and packaging requirements

Lead strategic methodology improvements including infrastructure-as-code and continuous integration strategies that benefit 100+ hardware engineers

Qualification

PythonBash scriptingSystemVerilog/VerilogCPU microarchitectureEDA toolsGit/GitLab CI/CDAI-enhanced productivitySystems thinking

Required

5+ years in semiconductor IP development, ASIC/SoC design, or related hardware engineering disciplines with BS/MS in Computer Engineering, Electrical Engineering, or Computer Science

Expert-level Python and Bash scripting for automation and tooling development, with advanced Git/GitLab proficiency including CI/CD pipelines

Proficient in SystemVerilog/Verilog with ability to review and debug RTL implementations across complex design hierarchies

Deep understanding of CPU microarchitecture (pipeline design, cache hierarchies, memory subsystems) and industry-standard interconnect protocols (AMBA AXI/AHB/APB, TileLink, Wishbone)

Experience with EDA tools: simulators (VCS, Xcelium, Verilator), lint tools (SpyGlass Lint), physical design tools (Formality, Design Compiler)

AI-enhanced productivity: Leveraging LLM tools (Cursor, GitHub Copilot, ChatGPT, Claude) to accelerate development, debugging, and documentation—you're 10x-ing yourself with AI

Systems thinker who automates reflexively and sees how git hooks connect to release quality connects to customer satisfaction