GE Aerospace · 3 days ago
Lead Design Engineer Custom Logic
GE Aerospace is a leader in technology development and innovation, and they are seeking a Lead Custom Logic Engineer to develop design solutions for complex project challenges. The role involves leading project plans, executing custom logic development, and ensuring compliance with certification requirements.
Responsibilities
Perform tasks for any portion in the design lifecycle of an FPGA in the Xilinx, Microsemi and other product families
Design FPGA, ASIC and CPLD devices for avionics hardware applications, including innovation resulting in patent applications
Responsible for VHDL design using appropriate tools to perform design and simulation of the FPGA
Responsible for requirements development and management in DOORs along with the preparation of appropriate DO-254 certification artifacts
Define project plans for executing custom logic development, including scheduling and cost management objectives
Develop bids and proposals and define complex architectures for your product area
Uses judgment to make decisions or solve moderately complex tasks or problems in hardware design, manufacturing, or technology
Uses technical experience and expertise for data analysis to support development recommendations
Uses multiple internal and limited external sources outside of own function to arrive at decisions
Acts as a resource for colleagues with less experience
May lead small projects with moderate risks and resource requirements
Explains difficult or sensitive information; works to build consensus
Developing persuasion skills required to influence others on topics within field
Responsible for working multiple projects with multiple teams in parallel
Ensure proper documentation of technical data generated for the assigned projects and/or tasks, consistent with engineering policies and procedures
Qualification
Required
This position requires U.S. citizenship status
Bachelor's degree from an accredited university/college in Electrical or Computer Engineering with a minimum of 10 years of professional experiences in design
This position offers a hybrid work arrangement and can be based in one of our three offices: Clearwater, FL; Melbourne, FL; or Grand Rapids, MI. The role requires a presence in the office three days a week (Tuesday–Thursday). An extensive corporate relocation package is available for eligible candidates
Preferred
Master of Science in Electrical or Computer Science Engineering
Minimum of 5 years of experience in computing product development containing cSoC device architectures
Preferred candidate has knowledge of high-speed data interfaces and functions used in computing applications such as PCIe, AXI bus, SERDES, DMA, etc
Experience with avionics interfaces and protocols such as MIL-STD-1553, A429, A664, and TSN
Experience with Intel Quartus, Lattice Diamond, Microsemi Libero and Xillinx Vivado
Experience in VHDL and UVM Test Benches
Experience with the Mentor Graphics Expedition Enterprise and Hyperlinx PI/SI
Strong oral and written communication skills. Ability to document, plan, market, and execute programs
Strong interpersonal and leadership skills
Experience in the Mil/Aero/avionics, DO-254 and Civil FFA Certification
Ability to break down complex problems and apply critical thinking
Benefits
Healthcare benefits include medical, dental, vision, and prescription drug coverage
Access to a Health Coach from GE Aerospace
Employee Assistance Program, which provides 24/7 confidential assessment, counseling and referral services
GE Aerospace Retirement Savings Plan
401(k) savings plan with company matching contributions and company retirement contributions
Access to Fidelity resources and planning consultants
Tuition assistance
Adoption assistance
Paid parental leave
Disability insurance
Life insurance
Paid time-off for vacation or illness
Company
GE Aerospace
GE Aerospace is a provider of jet and turboprop engines, as well as integrated systems.
Funding
Current Stage
Public CompanyTotal Funding
$2.01BKey Investors
JobsOhioUS Department of EnergyAir Force Research Laboratory
2025-07-22Post Ipo Debt· $2B
2025-01-10Grant· $9M
2024-04-02IPO
Leadership Team
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