Texas Instruments · 2 months ago
Chip Architect
FORE 12500 TI Boulevard, Dallas, TX, 75243, US
Full-time
Onsite
Senior LevelTexas Instruments is seeking a talented Chip Architect to join their ACS team which develops cutting edge ASSP ICs. This role involves architecting mixed-signal chips and optimizing functionality and performance by partitioning digital and analog design blocks.
ComputerDSPSemiconductor
Responsibilities
Work with our customers, systems, analog/digital design, layout, verification, and test/validation teams to define the chip architecture to meet all project requirements
Own the chip top-level integration. Drive the integration process from architectural definition through PG, ensuring robust functionality, parametric compliance, and on-time first-pass success
Partition functionality between analog and digital domains according to best-practices, to be rigorously verifiable (Design for Verification), and to be testable (Design for Test)
Architect high-speed clock and data paths across analog and digital domains to meet chip performance objectives and to allow for robust sign-off. Define the methodology for sign-off of clock and data paths across analog and digital domains (e.g. CDC, RDC, formal, extractions, STA, margining, jitter, cross-talk, EMIR, aging, GLS, DMS, AMS, Spectre and Xcelium simulations, etc.)
Enable rigorous DMS and AMS verification through design partitions that are friendly to modeling, and by driving a rigorous block modeling methodology. Create and maintain models and/or drive model creation with stakeholders. Create and maintain flows to manage netlisting and config hierarchy selection for AMS and DMS flows (e.g. schematic netlist, real-number model, simple logical model, Verilog-AMS electrical or wreal model, RTL, Gates/SDF, etc.)
Define block handoff requirements and acceptance checks for analog IP and digital IP. Drive sign-off checks. Increase the use of automation to ensure consistency in results and to reduce manual effort
Effectively work with project management and cross-functional team members to ensure all project deliverables meet requirements and schedules, and to ensure smooth integration according to plan
Qualification
Required
Bachelor's Degree
Experience in architecting mixed-signal chips
Experience in partitioning digital and analog design blocks
Knowledge of high-speed clock and data paths
Experience in Design for Verification and Design for Test
Ability to work with customers, systems, analog/digital design, layout, verification, and test/validation teams
Experience in chip top-level integration
Knowledge of methodologies for sign-off of clock and data paths across analog and digital domains
Experience with DMS and AMS verification
Ability to create and maintain models and/or drive model creation with stakeholders
Experience in managing netlisting and config hierarchy selection for AMS and DMS flows
Ability to define block handoff requirements and acceptance checks for analog IP and digital IP
Experience in driving sign-off checks
Ability to work with project management and cross-functional team members
Company
Texas Instruments
Texas Instruments is a global semiconductor company that manufactures, designs, tests, and sells embedded and analog processing chips.
Founded in 1930
10001+ employees
H1B Sponsorship
Texas Instruments has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (189)
2024 (184)
2023 (148)
2022 (222)
2021 (165)
2020 (179)
Funding
Current Stage
Public CompanyTotal Funding
$13.61BKey Investors
U.S. Department of Commerce
2025-05-20Post Ipo Debt· $1.2B
2024-12-20Grant· $1.61B
2024-05-28Post Ipo Equity· $2.5B
Leadership Team
Richard Templeton
President and Chief Executive Officer
Krunali Patel
Senior vice president and chief information officer
Recent News
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2026-01-13
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