Texas Instruments · 13 hours ago
Chip Architect
Dallas, TX
Full-time
Onsite
Senior Level, Lead/Staff
10+ years expTexas Instruments is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips. They are seeking a talented Chip Architect to join their ACS team, where the individual will play a key role in architecting mixed-signal chips and optimizing functionality and performance for high-speed clock and data paths.
ComputerDSPSemiconductor
Responsibilities
Work with our customers, systems, analog/digital design, layout, verification, and test/validation teams to define the chip architecture to meet all project requirements
Own the chip top-level integration. Drive the integration process from architectural definition through PG, ensuring robust functionality, parametric compliance, and on-time first-pass success
Partition functionality between analog and digital domains according to best-practices, to be rigorously verifiable (Design for Verification), and to be testable (Design for Test)
Architect high-speed clock and data paths across analog and digital domains to meet chip performance objectives and to allow for robust sign-off. Define the methodology for sign-off of clock and data paths across analog and digital domains (e.g. CDC, RDC, formal, extractions, STA, margining, jitter, cross-talk, EMIR, aging, GLS, DMS, AMS, Spectre and Xcelium simulations, etc.)
Enable rigorous DMS and AMS verification through design partitions that are friendly to modeling, and by driving a rigorous block modeling methodology. Create and maintain models and/or drive model creation with stakeholders. Create and maintain flows to manage netlisting and config hierarchy selection for AMS and DMS flows (e.g. schematic netlist, real-number model, simple logical model, Verilog-AMS electrical or wreal model, RTL, Gates/SDF, etc.)
Define block handoff requirements and acceptance checks for analog IP and digital IP. Drive sign-off checks. Increase the use of automation to ensure consistency in results and to reduce manual effort
Effectively work with project management and cross-functional team members to ensure all project deliverables meet requirements and schedules, and to ensure smooth integration according to plan
Qualification
Required
10+ years of experience as a digital designer, including 5+ years as a design lead
A thorough understanding of digital logic design, timing, and the Verilog and SystemVerilog languages
Experience in design and verification of high-speed clock and data paths, including sign-off checks such as CDC, RDC, STA, and GLS
Solid understanding of analog design, and the capability to explain operation at schematic-level
Strong understanding of mixed-signal and digital verification flows (AMS / DMS / TLDV / DDV), and modeling of analog blocks
Strong leadership, communication, cross-team collaboration skills, and customer-facing skills
Strong analytical and problem-solving skills
Ability to work in a fast-paced and rapidly-changing environment
Preferred
Experience as a chip architect or integration lead, or experience of closely working with individuals in these roles
Experience in design or verification of PLLs, DLLs, and clock/data recovery (CDR) circuits
Direct experience as a systems engineer, or experience of closely working with a systems engineer or a systems architect
Experience in modeling analog blocks such as real-number modeling (SystemVerilog EEnet or Verilog-AMS wreal), logical modeling (Verilog, SystemVerilog), or electrical modeling (Verilog-AMS)
Experience with top-level timing closure across digital and analog boundaries
Experience with creating and maintaining chip schematics/symbols in Cadence Virtuoso
Benefits
Competitive pay and benefits designed to help you and your family live your best life
Company
Texas Instruments
Texas Instruments is a global semiconductor company that manufactures, designs, tests, and sells embedded and analog processing chips.
10001+ employees
H1B Sponsorship
Texas Instruments has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
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Trends of Total Sponsorships
2025 (189)
2024 (184)
2023 (148)
2022 (222)
2021 (165)
2020 (179)
Funding
Current Stage
Public CompanyTotal Funding
$13.61BKey Investors
U.S. Department of Commerce
2025-05-20Post Ipo Debt· $1.2B
2024-12-20Grant· $1.61B
2024-05-28Post Ipo Equity· $2.5B
Leadership Team
Richard Templeton
President and Chief Executive Officer
Krunali Patel
Senior vice president and chief information officer
Recent News
2026-01-09
2026-01-07
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