AMD · 3 weeks ago
Lead Design Verification Engineer
Santa Clara, CA
Full-time
Hybrid
Lead/Staff
$221K/yr - $332K/yrAMD is a company that builds products for next-generation computing experiences. They are seeking a seasoned Lead Design Verification Engineer to drive the verification strategy and execution for high-performance networking chips, leading verification teams and collaborating with various stakeholders.
AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor
No H1B
Responsibilities
Ownership of verification strategy for one or more major IP blocks or subsystems within a complex networking ASIC
Architect and implement testbenches using UVM/SystemVerilog, ensuring maximum coverage and quality
Develop and maintain test plans, coverage models, and scoreboards to ensure comprehensive verification of all design features
Lead and mentor a team of DV engineers — drive reviews, define milestones, and ensure high-quality deliverables
Collaborate closely with design, architecture, and software teams to define verification requirements and debug issues across the full chip
Develop and maintain automation and regression infrastructure, including CI/CD integration
Drive coverage closure and signoff for IP and SoC-level verification
Contribute to methodology improvements, verification IP reuse, and best practices across the DV organization
Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
Qualification
Required
Expertise in verifying networking chip
Deep expertise in SoC/ASIC verification
Strong knowledge of networking protocols and architectures
Proven ability to lead verification teams in a fast-paced environment
Ownership of verification strategy for one or more major IP blocks or subsystems within a complex networking ASIC
Architect and implement testbenches using UVM/SystemVerilog, ensuring maximum coverage and quality
Develop and maintain test plans, coverage models, and scoreboards to ensure comprehensive verification of all design features
Lead and mentor a team of DV engineers — drive reviews, define milestones, and ensure high-quality deliverables
Collaborate closely with design, architecture, and software teams to define verification requirements and debug issues across the full chip
Develop and maintain automation and regression infrastructure, including CI/CD integration
Drive coverage closure and signoff for IP and SoC-level verification
Contribute to methodology improvements, verification IP reuse, and best practices across the DV organization
Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
Preferred
Proven line management experience, including hiring, mentoring, and performance management of DV engineers
Demonstrated ability to build and lead high-performing verification teams, setting goals and driving execution across projects
Experience with chip-level verification for networking ASICs, switches, or routers
Familiarity with traffic generators, packet-level verification, and network protocol stacks
Knowledge of SystemC, C testbenches, or hardware/software co-verification
Exposure to emulation or FPGA prototyping environments (e.g., Palladium, Veloce)
Prior experience leading cross-site or multi-IP verification efforts
Strong communication, collaboration, and leadership skills with the ability to influence technical direction across disciplines
Bachelor's or Master's degree in related discipline preferred
Benefits
AMD benefits at a glance.
Company
AMD
Advanced Micro Devices is a semiconductor company that designs and develops graphics units, processors, and media solutions.
Founded in 1969
10001+ employees
Funding
Current Stage
Public CompanyTotal Funding
unknownKey Investors
OpenAIDaniel Loeb
2025-10-06Post Ipo Equity
2023-03-02Post Ipo Equity
2021-06-29Post Ipo Equity
Leadership Team
Lisa Su
Chair & CEO
Mark Papermaster
CTO and EVP
Recent News
Morningstar.com
2026-01-11
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