AMD ยท 1 day ago
Physical Design Methodology Engineer
Santa Clara, CA
Full-time
Onsite
Mid Level
$191K/yr - $287K/yrAMD is a company focused on building innovative products that enhance computing experiences across various domains including AI and data centers. The role involves working within the Graphics and Engineering group to develop physical design methodologies for advanced computing systems, collaborating with various engineering teams to ensure successful chip design and implementation.
AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor
No H1B
Responsibilities
Physical design and signoff methodology development for advanced nodes and High performance
Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC
Full chip / sub-system/ Tile level timing analysis with bleeding edge STA methodologies
Full chip / sub system level Clock tree synthesis and advanced clock tree construction and analysis
Block and top level Formal verification, Physical Verification and chip finishing methodologies
Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion, IRdrop and logic equivalence
Statistical and Static Timing Analysis, Variation aware analysis, stdcell Library characterization enhancements
Developing and Integrating ML and LLM applications for Physical Design and Analysis flows
Performing data analysis and identifying design trends
Customizing and implementing solutions for new challenges
Collaborating with multi-site engineering teams to reach project goals
Hands-on in reference flows, excellent debugging skills
Maintain and update technology collaterals
Qualification
Required
Physical design and signoff methodology development for advanced nodes and High performance
Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC
Full chip / sub-system/ Tile level timing analysis with bleeding edge STA methodologies
Full chip / sub system level Clock tree synthesis and advanced clock tree construction and analysis
Block and top level Formal verification, Physical Verification and chip finishing methodologies
Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion, IRdrop and logic equivalence
Statistical and Static Timing Analysis, Variation aware analysis, stdcell Library characterization enhancements
Developing and Integrating ML and LLM applications for Physical Design and Analysis flows
Performing data analysis and identifying design trends
Customizing and implementing solutions for new challenges
Collaborating with multi-site engineering teams to reach project goals
Hands-on in reference flows, excellent debugging skills
Maintain and update technology collaterals
Bachelors or Masters degree in computer engineering/Electrical Engineering
Preferred
Experience in ASIC Physical Design and/or CAD development
Hands-on experience with Place and Route, Timing Analysis, and Physical Verification tools from Synopsys, Cadence, like ICC2, Fusion Compiler, DSO.AI, Innovus, Cerebrus, Primetime, Primeshield, PT-PX, Formality, Conformal, RedHawk, etc
Experience in 5nm and below technologies
Script development, scripting (TCL, Perl, Python, Pandas), ML/AI techniques
Knowledge and Experience in ML and LLM
Experience with data analytics applications, database management
Benefits
AMD benefits at a glance.
Company
AMD
Advanced Micro Devices is a semiconductor company that designs and develops graphics units, processors, and media solutions.
Founded in 1969
10001+ employees
Funding
Current Stage
Public CompanyTotal Funding
unknownKey Investors
OpenAIDaniel Loeb
2025-10-06Post Ipo Equity
2023-03-02Post Ipo Equity
2021-06-29Post Ipo Equity
Leadership Team
Lisa Su
Chair & CEO
Mark Papermaster
CTO and EVP
Recent News
2026-01-13
Morningstar.com
2026-01-11
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