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Amazon · 2 months ago

Senior Mixed-Signal Silicon Engineer

San Diego, California, USA

Full-time

Onsite

Senior Level

$143K/yr - $248K/yr

7+ years exp

Amazon is launching Project Kuiper, an initiative to provide high-speed broadband connectivity through a constellation of Low Earth Orbit satellites. The Senior Mixed-Signal Silicon Engineer will work with a cross-disciplinary team to design and optimize mixed-signal circuit blocks, focusing on power and cost optimization for system performance.

Artificial Intelligence (AI)DeliveryE-CommerceFoundational AIRetail

No H1B

U.S. Citizen Only

Responsibilities

Design & optimize high-speed (>800Msps) medium resolution (5-8 bits) DACs & ADCs and other analog/mixed-signal blocks in deeply scaled CMOS technologies

Explore circuit architectures for power/area/performance trade-offs

Perform circuit layout, parasitic extraction and simulation

Collaborate with cross-functional teams to define analog/digital interface requirements and define supporting digital functions

Specify bench and production test plans for your design and enable volume production

Qualification

Mixed-signal designHigh-speed circuit designCMOS technologiesMatlabVerilog-ASERDESData convertersCadence VirtuosoEffective communicationTeam collaborationProblem-solving

Required

Master's degree in Electrical or Communications Engineering or a related field

7+ years of experience in mixed-signal design, preferably in an advanced node

Experience in taking designs to volume production

Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum

Preferred

10+ years of experience in high-speed, low-power mixed-signal circuit design, layout and verification in the following: FinFET, SOI, BiCMOS, and Bulk CMOS technologies

Knowledge of time-interleaved ADC architectures, digitally-assisted analog techniques

Proficient in modeling circuits using Matlab, Verilog-A

Knowledgeable in SERDES, data converter clock distribution design and jitter/phase noise concepts

Proficiency with digital and mixed signal simulators, for example Incisive/Xcelium, VCS, AMS Designer

Knowledge of the Cadence Virtuoso Design Framework, Virtuoso Schematic Editor, and Analog Design Environment (Explorer/Assembler)

Knowledge of programming in Python, Perl, and SKILL

Effective written and verbal communication skills