Advanced Microdevices Pvt. Ltd. (India) ยท 2 months ago
Physical Design Methodology Engineer
Santa Clara, CA
Full-time
Hybrid
Mid LevelAdvanced Micro Devices, Inc is committed to building products that accelerate next-generation computing experiences. The Physical Design Methodology Engineer will be responsible for developing methodologies for physical design, collaborating with various engineering teams to ensure first pass silicon success, and integrating ML and LLM applications into design flows.
BiopharmaBiotechnologyIndustrialManufacturing
Responsibilities
Physical design and signoff methodology development for advanced nodes and High performance
Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC
Full chip / sub-system/ Tile level timing analysis with bleeding edge STA methodologies
Full chip / sub system level Clock tree synthesis and advanced clock tree construction and analysis
Block and top level Formal verification, Physical Verification and chip finishing methodologies
Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion, IRdrop and logic equivalence
Statistical and Static Timing Analysis, Variation aware analysis, stdcell Library characterization enhancements
Developing and Integrating ML and LLM applications for Physical Design and Analysis flows
Performing data analysis and identifying design trends
Customizing and implementing solutions for new challenges
Collaborating with multi-site engineering teams to reach project goals
Hands-on in reference flows, excellent debugging skills
Maintain and update technology collaterals
Qualification
Required
Bachelors or Masters degree in computer engineering/Electrical Engineering
Highly accurate and detail-oriented
Good communication and problem-solving skills
Physical design and signoff methodology development for advanced nodes and High performance
Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC
Full chip / sub-system/ Tile level timing analysis with bleeding edge STA methodologies
Full chip / sub system level Clock tree synthesis and advanced clock tree construction and analysis
Block and top level Formal verification, Physical Verification and chip finishing methodologies
Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion, IRdrop and logic equivalence
Statistical and Static Timing Analysis, Variation aware analysis, stdcell Library characterization enhancements
Developing and Integrating ML and LLM applications for Physical Design and Analysis flows
Performing data analysis and identifying design trends
Customizing and implementing solutions for new challenges
Collaborating with multi-site engineering teams to reach project goals
Hands-on in reference flows, excellent debugging skills
Maintain and update technology collaterals
Preferred
Experience in ASIC Physical Design and/or CAD development
Hands-on experience with Place and Route, Timing Analysis, and Physical Verification tools from Synopsys, Cadence, like ICC2, Fusion Compiler, DSO.AI, Innovus, Cerebrus, Primetime, Primeshield, PT-PX, Formality, Conformal, RedHawk, etc
Experience in 5nm and below technologies
Script development, scripting (TCL, Perl, Python, Pandas), ML/AI techniques
Knowledge and Experience in ML and LLM
Experience with data analytics applications, database management
Benefits
AMD benefits at a glance.
Company
Advanced Microdevices Pvt. Ltd. (India)
Advanced Microdevices (mdi) is a leader in innovative membrane technologies.
Founded in 1976
501-1000 employees
Funding
Current Stage
Late StageLeadership Team
Nalini Kant Gupta
Founder & Managing Director
Recent News
2024-10-18
2024-10-16
Company data provided by crunchbase