Altera · 2 months ago
EMIR Technical Lead
San Jose, California, United States
Full-time
Onsite
Senior Level, Lead/Staff
10+ years expAltera is a company specializing in advanced technology solutions, and they are seeking an EMIR Technical Lead to join their Physical Design organization. This role involves leading EMIR methodology and signoff, collaborating across various teams to achieve performance and power goals, and mentoring junior engineers.
Enterprise SoftwareManufacturingSemiconductorSoftware
Responsibilities
Lead and execute power/EMIR methodology, implementation, and signoff for all designs within the company
Work closely with physical design implementation (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, ECOs, extraction, and signoff preparation) to ensure EMIR convergence at all stages
Apply PPA optimization techniques (performance/timing closure, power reduction, area efficiency) across block and full-chip hierarchies
Collaborate with front-end design, architecture, and CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets, and DFT insertions are met
Develop and enhance EMIR flows, methodologies, scripts, and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR, and reduce manual intervention
Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domain management for programmable regulation, and yield optimization
Partner with manufacturing and packaging teams to ensure designs are manufacturable (DFM/DFY), meet yield targets, and support high-volume production
Debug physical design issues and work with CAD tool vendors and internal tool teams to drive tool enhancements or implement workarounds
Mentor junior engineers, contribute to design reviews, document flows, and promote continuous process improvement
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
10+ years of experience in EMIR signoff and closure at chip and block/super-block level (power/IR analysis, signal/power integrity reports, and corrective actions)
Timing closure (minimum at block/super-block level)
Power estimation (minimum at block/super-block level)
Digital/SoC physical design (from synthesis through P&R to signoff)
Proficiency with industry-standard EDA tools (e.g., Redhawk/Voltus, Totem/Voltus-FI, Synopsys IC Compiler/Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high-speed digital ASIC/SoC implementation
Strong scripting/programming skills (TCL, Python, Perl, shell) for flow automation and productivity enhancement
Experience collaborating with front-end teams (RTL, architecture), CAD/EDA tool teams, and manufacturing/packaging teams
Knowledge of bump planning, RDL routing, MiMCap planning, and ESD signoff
Efficient I/O budgeting (chip/partitions/blocks)
Preferred
Experience in PNR flow and signoff: floorplanning, CTS, placement, routing, power domain gating, clock domain crossing, multi-power domain design, timing closure, ECOs, and DRC/LVS/DFM issues
Familiarity with advanced process nodes (7nm, 5nm or smaller) or FPGA/programmable logic device flows
Understanding of FPGA architecture: routing fabrics, programmable logic blocks (PLBs), on-chip networks, I/O rings, and static/dynamic reconfiguration
Knowledge of low-power design methodologies, power grid design, power gating, multi-voltage domain implementation, and power signoff flows
Prior exposure to full-chip integration flows (block-to-chip convergence) and high-frequency (1 GHz+) timing closure
Experience in high-volume manufacturing environments, including yield and DFM/DFY considerations
Proven ability to mentor or lead small physical design sub-teams or own major P&R blocks
Company
Altera
Altera provides programmable logic devices and design software for various applications. It is a sub-organization of Intel.
1001-5000 employees
H1B Sponsorship
Altera has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (67)
Funding
Current Stage
Public CompanyTotal Funding
unknown2025-04-14Acquired
1988-03-31IPO
Leadership Team
Raghib Hussain
Chief Executive Officer
Recent News
Business Wire
2025-11-25
2025-11-19
Company data provided by crunchbase