Etched · 1 week ago
Performance Engineer
San Jose, CA
Full-time
Onsite
Mid, Senior LevelEtched is building AI chips that are hard-coded for individual model architectures. The Performance Engineer will develop performance models and analyze deep learning workloads to optimize the Sohu architecture, collaborating with hardware architects and driving co-optimization efforts.
Artificial Intelligence (AI)ComputerHardwareSemiconductor
Responsibilities
Develop comprehensive performance models and projections for Sohu's transformer-specific architecture across varying workloads and configurations
Profile and analyze deep learning workloads on Sohu to identify micro-architectural bottlenecks and optimization opportunities
Build analytical and simulation-based models to predict performance under different architectural configurations and design trade-offs
Collaborate with hardware architects to inform micro-architectural decisions based on workload characteristics and performance analysis
Drive hardware/software co-optimization by identifying opportunities where architectural features can unlock significant performance improvements
Characterize and optimize memory hierarchy performance, interconnect utilization, and compute resource efficiency
Develop performance benchmarking frameworks and methodologies specific to transformer inference workloads
Build detailed roofline models and performance projections for Sohu across diverse transformer architectures (Llama, Mixtral, etc.)
Profile production inference workloads to identify and eliminate micro-architectural bottlenecks
Analyze memory bandwidth, compute utilization, and interconnect performance to guide next-generation architecture decisions
Develop performance modeling tools that predict chip behavior across different batch sizes, sequence lengths, and model configurations
Characterize the performance impact of architectural features like specialized datapaths, memory hierarchies, and on-chip interconnects
Compare Sohu's architectural efficiency against conventional GPU architectures through detailed bottleneck analysis
Inform hardware design decisions for future generations (Caelius and beyond) based on workload analysis and performance projections
Qualification
Required
Deep expertise in computer architecture and micro-architecture, particularly for accelerators or domain-specific architectures
Strong performance modeling and analysis skills with experience building analytical or simulation-based performance models
Experience profiling and optimizing deep learning workloads on hardware accelerators (GPUs, TPUs, ASICs, FPGAs)
Strong understanding of hardware/software co-design principles and cross-layer optimization
Solid foundation in digital circuit design and how micro-architectural decisions impact performance
Experience with reconfigurable or heterogeneous architectures
Ability to reason quantitatively about performance bottlenecks across the full stack from circuits to workloads
Preferred
PhD or equivalent research experience in Computer Architecture or related fields
Experience with ASIC, FPGA, or CGRA-based accelerator development
Published research in computer architecture, ML systems, or hardware acceleration
Deep knowledge of GPU architectures and CUDA programming model
Experience with architecture simulators and performance modeling tools (gem5, trace-driven simulators, custom models)
Track record of informing architectural decisions through rigorous performance analysis
Familiarity with transformer model architectures and inference serving optimizations
Benefits
Full medical, dental, and vision packages, with generous premium coverage
Housing subsidy of $2,000/month for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to West San Jose
Company
Etched
Building the hardware for superintelligence
Founded in 2022
51-200 employees
H1B Sponsorship
Etched has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (9)
2024 (11)
2023 (1)
Funding
Current Stage
Growth StageTotal Funding
$125.36MKey Investors
Primary Venture Partners
2024-06-25Series A· $120M
2023-05-16Seed· $5.36M
Leadership Team
Chris Zhu
Co-Founder
Robert Wachen
Co-Founder and President
Recent News
Google Patent
2025-04-02
Google Patent
2024-12-04
2024-12-02
Company data provided by crunchbase