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General Dynamics Mission Systems · 1 month ago

Sr ASIC FPGA Verification Engineer

Scottsdale, AZ

Full-time

Hybrid

Mid, Senior Level

$114K/yr - $127K/yr

2+ years exp

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products, and services that enable customers to successfully execute missions across all domains of operation. They are seeking a Senior ASIC FPGA Verification Engineer responsible for the definition, design, verification, and documentation for ASIC and/or FPGA developments, while also contributing to process improvements and project completion.

AerospaceBusiness Information SystemsInformation ServicesInformation TechnologyNational SecuritySensor

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments

Determines architecture, system simulation and detailed design approach

Defines module interfaces and all aspects of device design and simulation

Creates test and simulation plans that establish functional criteria

Verifies test results and analyzes performance

May also review vendor capabilities and simulation tools

Participates in the improvement of the ASIC/FPGA organizational processes

Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle

May provide leadership and/or direction to lower level employees

Independently determines approach to solutions

Contributes to the completion of major programs and projects

Plans and executes project tasks for activities described above

Qualification

RTL simulation toolsSystem VerilogUniversal Verification MethodologyScripting languagesRequirements-based verificationFormal verification toolsMulti-taskingTeam collaborationCommunication skillsProblem solving

Required

Requires a Bachelor's degree in Reliability, Electrical, Mechanical or Materials Engineering, or a related Science, Engineering, Technology or Mathematics field

Also requires 2+ years of job-related experience, or a Master's degree and 6 months of job-related experience

Department of Defense TS/SCI security clearance is preferred at time of hire

Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire

Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information

Due to the nature of work performed within our facilities, U.S. citizenship is required

Proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theories

Proficient in the principles and techniques of ASIC/FPGA design and the design process

Keeps abreast of technology trends

Proficient awareness of business objectives and Engineering's role in achieving

Proficient in Microsoft Office applications

Proficient written and verbal communications skills

Ability to think creatively

Ability to multi-task

Proficient skill in communicating issues, impacts, and corrective actions

Regular contact with senior levels of internal work groups

Works under limited direction

Contact with project leaders and other professionals within the Engineering department and with project teams across the company

Some contact with external customers

Preferred

In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment

In-depth knowledge of System Verilog object oriented programming and the Universal Verification Methodology (UVM)

Understands UVM Testbench Architectures

Comfortable using and developing UVM agents, bus functional models

Understands different types of coverage, usage of cover classes, cover points, etc

Experience with predictive testbench components, functional coverage and assertions

Experience with constrained random testing

Experience with the Register Abstraction Layer

Familiarity with requirements-based verification, requirement tracing, and developing requirement verification strategies etc

Experience with scripting languages such as Linus shell scripts, TCL, Python

Familiarity with using Formal Verification tools, code coverage, writing waivers etc

Familiarity with the following are also helpful: Questa Verification IP (QVIP), Developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs, AXI protocols, PCIe, Space Wire, and Ethernet interfaces, DSP functions and common signal processing components, Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration, Continuous Integration features of GITLab

Clear understanding of embedded micro-processing systems, FPGA Design and Verification using VHDL, and digital circuit analysis and design

Collaborative, creative thinker with high proficiency in technical problem solving

Team player with effective communication and presentation skills

Experience designing high speed interfaces and complex memory designs

Commitment to ongoing professional development for yourself and others

Benefits

401k matching

Flex time off

Paid parental leave

Healthcare benefits

Health & wellness programs

Employee resource and social groups

Company

General Dynamics Mission Systems

Glassdoor3.9

General Dynamics Mission Systems designs and delivers critical systems and products for defense and cybersecurity customers. It is a sub-organization of General Dynamics.

Founded in 1952

Fairfax, Virginia, USA

10001+ employees