Senior Principal ASIC Static Timing Engineer jobs in United States
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Northrop Grumman Australia · 1 month ago

Senior Principal ASIC Static Timing Engineer

Northrop Grumman is a leading company in technological advancements, seeking a Static Timing Engineer to join their Digital Technologies department. The role involves performing static timing analysis on digital designs, identifying violations, and collaborating with various teams to optimize design performance and methodologies.

Defense & Space
badNo H1BnoteSecurity Clearance RequirednoteU.S. Citizen Onlynote

Responsibilities

Responsible for static timing analysis on digital designs to ensure timing requirements are met
Identify timing violations and perform or propose changes to fix them
Work closely with design, verification, design-for-test and physical design teams to optimize the timing and improve design performance
Develop and validate timing constraints and ensure they are correctly implemented
Develop and maintain timing methodologies and flows for efficient timing analysis and closure
Conduct design reviews to provide recommendations for meeting timing goals
Troubleshoot timing issues and provide effective solutions
Stay up-to-date with industry trends and advancements in static timing analysis tools and methodologies

Qualification

Static Timing AnalysisCadence/Synopsys ToolsHDL (VHDL/Verilog/SystemVerilog)Scripting LanguagesMulti-mode Multi-corner AnalysisTechnical Problem SolvingEffective Communication

Required

Bachelor's degree with 8 years of experience, a Master's degree with 6 years of experience or a Ph.D. with 4 years of experience in Science, Technology, Engineering, Mathematics, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree
U.S. Citizenship is required
Ability to obtain/maintain an active Secret clearance and a Special Program Access (SAP) prior to start
4 years of experience with Cadence and/or Synopsys tools for Static Timing Analysis
4 years of experience in static timing analysis, noise analysis and timing constraint development
4 years of experience in multi-mode, multi-corner analysis and optimization
4 years of experience in scripting languages such as Tcl, Python, or Perl
4 years of working knowledge in HDL (VHDL/Verilog/SystemVerilog)
4 years of experience in the full product life cycle of ASIC Design

Preferred

Master's Degree in Electrical or Computer Engineering
Knowledge of Synthesis, Place & Route (P&R), and Design-for-Test (DFT) methodologies
Active DoD Secret Clearance or higher
Effective communication and presentation skills and high proficiency in technical problem solving

Benefits

Medical, Dental & Vision coverage
401k
Educational Assistance
Life Insurance
Employee Assistance Programs & Work/Life Solutions
Paid Time Off
Health & Wellness Resources
Employee Discounts

Company

Northrop Grumman Australia

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Northrop Grumman Australia is the Australia-based arm of Northrop Grumman Corporation and committed to generating long-term prosperity, investing in advanced Research & Development, sovereign and exportable Intellectual Property, high-quality jobs and long-term technology leadership across the Commonwealth.

Funding

Current Stage
Late Stage
Company data provided by crunchbase