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Northrop Grumman · 1 month ago

Senior Principal ASIC Static Timing Engineer

Morrisville, NC

Full-time

Onsite

Senior Level, Lead/Staff

$144K/yr - $216K/yr

6+ years exp

Northrop Grumman is a leader in technological advancements, seeking a Static Timing Engineer to join their Digital Technologies department. The role involves static timing analysis on digital designs, identifying timing violations, and collaborating with various teams to optimize design performance.

AerospaceData IntegrationManufacturingRemote SensingSecurity

Growth Opportunities

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Responsible for static timing analysis on digital designs to ensure timing requirements are met

Identify timing violations and perform or propose changes to fix them

Work closely with design, verification, design-for-test and physical design teams to optimize the timing and improve design performance

Develop and validate timing constraints and ensure they are correctly implemented

Develop and maintain timing methodologies and flows for efficient timing analysis and closure

Conduct design reviews to provide recommendations for meeting timing goals

Troubleshoot timing issues and provide effective solutions

Stay up-to-date with industry trends and advancements in static timing analysis tools and methodologies

Qualification

Static Timing AnalysisCadence/Synopsys ToolsHDL (VHDL/Verilog/SystemVerilog)Scripting LanguagesMulti-mode Multi-corner AnalysisTechnical Problem SolvingEffective Communication

Required

Bachelor's degree with 8 years of experience, a Master's degree with 6 years of experience or a Ph.D. with 4 years of experience in Science, Technology, Engineering, Mathematics, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree

U.S. Citizenship is required

Ability to obtain/maintain an active Secret clearance and a Special Program Access (SAP) prior to start

4 years of experience with Cadence and/or Synopsys tools for Static Timing Analysis

4 years of experience in static timing analysis, noise analysis and timing constraint development

4 years of experience in multi-mode, multi-corner analysis and optimization

4 years of experience in scripting languages such as Tcl, Python, or Perl

4 years of working knowledge in HDL (VHDL/Verilog/SystemVerilog)

4 years of experience in the full product life cycle of ASIC Design