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Marvell Technology · 3 weeks ago

Principal Engineer - Design For Test (DFT)

Westborough, MA

Full-time

Onsite

Lead/Staff

$147K/yr - $220K/yr

10+ years exp

Marvell Technology is a leader in semiconductor solutions that drive data infrastructure across various industries. They are seeking a Digital IC Design Senior Principal Engineer to architect and implement DFT/Test on complex IP and SoC designs while mentoring a team and enhancing methodologies in the DFT domain.

DSPInternet of ThingsManufacturingSemiconductorWireless

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

The position will be responsible for architecting, leading and implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs

The execution involves Design-for-Test architecture definition, implementation of various DFT/DFX features, validation, IP-DFT, STA, pattern generation & post-silicon bring-up and debug for various designs/IPs in Custom/Compute space

In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs

The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test

This is a hands-on job

While leadership, mentoring, customer meetings, helping drive DFT architecture, inventing DFT solutions that address new scenarios, driving EDA vendors, are all an integral part of this role, the engineer will be executing on existing and new programs

Qualification

DFT architecture definitionASIC design experienceDFT execution functionsDigital circuit designDFT methodologiesSiemens/Synopsys toolsScripting skillsTeam leadershipProblem solvingCommunication

Required

Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience

Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience

Direct DFT experience with at least 5 years in the custom chip design business

Led the DFT execution on several ASICs. Was responsible for all DFT execution functions from architecture definition to tape out through silicon bring-up

Hands-on working experience in various stages of DFT-Execution: SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bring-up/Debug

Thorough knowledge on various DFT/Test architecture solutions and should have been involved in DFT-Architecture definition of at-least two monolithic designs

Thorough knowledge on various DFT/Test architecture solutions for 2.5D/3D IC design and should be involved in DFT-Architecture definition of at-least couple of MCM designs

Strong fundamentals in digital circuit design and logic design

Understanding of DFT flows and methodologies and experience with Siemens/Synopsys Tool set (Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC)

Proven track record of problem solving and innovation to meet challenging design requirements

Excellent team player and can work with different function leaders, across different geographies to define and execute the DFT project to completion

Excellent communications skill both verbal and written