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Marvell Technology · 1 month ago

Principal Technical IP Engineer - Manage 3rd Party IP Integration - DDR/LPDDR/GDDR/HBM/eMMC memory

Santa Clara, CA

Full-time

Onsite

Senior Level, Lead/Staff

$143K/yr - $214K/yr

7+ years exp

Marvell Technology is a leading semiconductor solutions provider that connects the world through innovative technology. The Principal Technical IP Engineer will manage 3rd party IP integration engineers and be involved in all stages of SoC development, ensuring compliance and integration of memory interface cores for clients.

DSPInternet of ThingsManufacturingSemiconductorWireless

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Manage 3rd party IP integration engineers to assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to our clients

Be involved in all stages of SoC development including defining core requirements, validating IP developer competence, overseeing core development, technology compliance, core integration, test compliance and silicon validation

Assist sales in winning bids by working with leading edge IP providers to meet customer requirements

Manage 3rd party developers in completing core designs and providing required design rules

Advise the Marvell design center on core integration into custom silicon designs and hold joint reviews with the design center and 3rd party IP provider

Post-silicon validation at customer sites will require a limited degree of travel

Develop statements of work, lead provider progress reviews, and use 3rd party developer problem reporting tools to drive to problem resolution

Assist with 8D follow-through for significant supplier issues

Qualification

DDR interfacesASIC design flowsProject managementDesign-For-Test conceptsCommunication skills

Required

BS degree in technical discipline with minimum 7 years of relevant experience

Proficient in understanding of DDR type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including the challenges associated with SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging

Proficient in project management tasks required to manage 3rd party developers

Broad-based exposure to ASIC design flows required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical checking

Good understanding of Design-For-Test concepts including DFT logic insertion, test generation, scan and embedded core testing

Good communication and customer management skills