Intel Corporation · 1 month ago
Principal Engineer - Silicon Packaging Architect
US, California, Santa Clara
Full-time
Hybrid
Lead/Staff
$215K/yr - $303K/yr
10+ years expIntel Corporation is seeking a Silicon Packaging Architect within its Central Engineering Group, responsible for bridging silicon design and advanced packaging. The role focuses on delivering high-performance, cost-effective solutions for next-generation SOCs and DDR PHY interfaces, involving collaboration with technical experts and hands-on simulations.
Semiconductors
Responsibilities
Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs
Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts
Conduct hands-on package extractions and simulations (signal integrity, power integrity) to assess package trace and electrical impacts, and perform risk assessments for bump-out strategies
Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases
Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed)
Focus on design, development, and architecture, not process or materials engineering
Qualification
Required
Experience in both silicon design (preferably mixed signal/analog) and packaging co-design
Background in DDR, SOC, or similar high-speed interface development
Hands-on expertise with bump mapping, floor planning, and packaging constraints
Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation
Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required
Individual contributor or principal engineer level preferred; management experience is not required
Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia)
Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master's or Ph.D. preferred)
10+ years in silicon and packaging co-design
Benefits
Competitive pay
Stock
Bonuses
Health
Retirement
Vacation
Company
Intel Corporation
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside.
10001+ employees
H1B Sponsorship
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Funding
Current Stage
Late StageLeadership Team
Brea Watts, MFA
Communications Manager, CEO
Carol Bartz
CEO
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