ASIC Verification Engineer jobs in United States
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Meta · 2 months ago

ASIC Verification Engineer

positionSunnyvale, CA
timeFull-time
remoteOnsite
seniorityNew Grad, Entry Level
money$136K/yr - $154K/yr

Meta Platforms, Inc. (Meta) builds technologies that help people connect, find communities, and grow businesses. They are seeking an ASIC Verification Engineer to develop and execute verification plans for ASIC designs, collaborating with design engineers to ensure comprehensive coverage and validation of design specifications.

Computer Software
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Comp. & Benefits

Responsibilities

Develop and execute verification plans for ASIC designs, ensuring comprehensive coverage and validation of design specifications
Collaborate with design engineers to understand design intent and identify potential verification challenges
Create and maintain testbenches and test cases using industry-standard verification languages and methodologies (e.g. SystemVerilog, UVM)
Perform simulation and debugging of ASIC designs to identify and resolve functional issues
Analyze and document verification results, providing feedback and recommendations for design improvements
Participate in design and verification reviews, contributing to the continuous improvement of verification processes and methodologies
Work closely with cross-functional teams, including design, architecture, and firmware, to ensure successful integration and functionality of ASIC designs

Qualification

ASIC verificationSystemVerilogUVMVerilogPythonEDA toolsDigital design conceptsCollaboration skillsDocumentation skills

Required

Master's degree (or foreign equivalent) in Electrical Engineering, Computer Engineering or a related field
Requires completion of a university-level course, research project, internship, or thesis in the following:
Developing and executing verification plans for digital designs
Using hardware description languages (e.g. Verilog) and verification languages (e.g. SystemVerilog) with in UVM (Universal Verification Methodology)
Creating and maintaining testbenches and test cases for ASIC verification
Debugging and resolving issues in digital designs through simulation and analysis
Understanding of digital design concepts and methodologies
Collaborating across design, emulation, and silicon validation teams for the development of robust test benches using SystemVerilog, and UVM methodologies
Using scripting skills in Python for test automation, environment setup, and process optimization
Utilizing EDA tools for simulation and verification (e.g. Cadence, Synopsys, Mentor Graphics)
Documenting verification processes and results for review and analysis
Engaging in design and verification review to analyze verification results, identify design issues, provide technical feedback, and recommend improvements to verification strategies and test plans

Benefits

Bonus
Equity
Benefits

Company

Meta

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Meta's mission is to build the future of human connection and the technology that makes it possible.
dateFounded in 2004
location
Menlo Park, CA, US
people-size10001+ employees
web-link
https://www.metacareers.com/

Funding

Current Stage
Late Stage

Leadership Team

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Kathryn Glickman
Director, CEO Communications
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Christine Lu
CTO Business Engineering NA
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